Heng Sheng Huang

Current conduction of 0.72 nm equivalent-oxide-thickness LaO/HfO2 stacked gate dielectrics

Metal-oxide-semiconductor capacitors (MOSCs) incorporating atomic layer deposited (ALD) LaO/HfO2 stacked gate dielectrics were fabricated, where the equivalent oxide thickness (EOT) of the high-k dielectrics is only 0.72 nm and the gate leakage (Jg) is as low as 6.8×10−2u2002A/cm2. Based on the analysis of the temperature dependence of the gate leakage current from 300 to 500 K, the main current conduction is found to be Schottky emission or Poole–Frankel emission. Moreover, the barrier height (ΦB) at TaC and HfLaO interface is estimated to be about 1.21 eV, and the trap energy level (Φt) is about 0.51 eV.

Electron detrapping in thin hafnium silicate and nitrided hafnium silicate gate dielectric stacks

The kinetics of zero-field and field-induced detrapping of electrons trapped in HfSixOy and HfSiON after positive bias stress on n+-polycrystalline silicon (polySi) gate of n-type metal-oxide-semiconductor (nMOS) capacitors are experimentally investigated. The self detrapping follows a simple logarithmic relation with time while field-induced detrapping upon reversing the stress voltage obeys a simple first-order exponential decay suggesting mono energetic shallow traps associated with tunnel emission of trapped electrons. Finally, our investigation raises questions about the validity of the widely used distributed capture cross section model of electron traps to explain the threshold voltage instability in MOS devices with hafnium silicate gate stacks.

Electrical performance of a-Si:H and poly-Si TFTs with heating stress

The amorphous channel (a-Si:H) TFT-LCD technology dominates the large-area flat panel display (FPD) market, but a-Si:H TFTs propose some adverse characteristics, especially in mobility. Therefore, developing poly-Si TFTs to promote mobility and implement the chip-on-glass (CoG) dream is indeed necessary. Using a green continuous-wave laser on amorphous silicon channel formed as poly-crystallization is a possible way in increasing the mobility value up to 450 cm2/V·sec. However, the electrical characteristics for them face the identical trend with temperature heating is degraded. However, the degradation of a-Si:H TFT is worse than that of poly-Si TFT when the device temperature is raised. In this study, the a-Si:H TFTs and poly-Si TFTs with furnace and green laser anneal were chosen. Comparing the transfer characteristics, subthreshold swing (S.S.), threshold voltage (Vth), ON/OFF ratio, field effect mobility (μFE), interface state density (Nit) with temperature effect, some trends are very interesting. The bulk traps were recovered by pseudo-crystallization with increasing temperature, and the transfer characteristics become better than the initial.

Positive bias temperature instability in p-type metal-oxide-semiconductor devices with HfSiON/SiO2 gate dielectrics

We present a detailed investigation on positive-bias temperature stress (PBTS) induced degradation of nitrided hafnium silicate (HfSiON)/SiO2 gate stack in n+-poly crystalline silicon (polySi) gate p-type metal-oxide-semiconductor (pMOS) devices. The measurement results indicate that gate dielectric degradation is a composite effect of electron trapping in as-fabricated as well as newly generated neutral traps, resulting a significant amount of stress-induced leakage current and generation of surface states at the Si/SiO2 interface. Although, a significant amount of interface states are created during PBTS, the threshold voltage (VT) instability of the HfSiON based pMOS devices is primarily caused by electron trapping and detrapping. It is also shown that PBTS creates both acceptor- and donor-like interface traps via different depassivation mechanisms of the Si3u2009≡u2009SiH bonds at the Si/SiO2 interface in pMOS devices. However, the number of donor-like interface traps ΔNitD is significantly greater than that ...

Punch-through and junction breakdown characteristics for uniaxial strained nano-node metal-oxide-semiconductor field-effect transistors on (100) wafers

In the nano-regime MOSFET devices, the punch-through effect is more distinct, retarding the reliability tolerance, such as electro-static discharge or latch-up applications. Through the measurement in various device lengths under contact-etch-stop-layer strain process or without strain effect for 45 nm complementary MOS process, the difference of punch-through effect and junction breakdown integrity were able to be classified and exhibited in design applications. After tested data analysis, the junction breakdown issue in PMOSFET was usually greater than that in NMOSFET due to the doping concentrations and the doping species. Generally, the junction breakdown value is independent of channel length variation except the existence of some damage close to the gate/source or gate/drain fringe. In addition, the punch-through voltage for PMOSFET as source/drain current IDS = 1 μA is also larger than that observed for NMOSFET.

On the reverse short-channel effect and threshold voltage roll-off controls for 90 nm node MOSFETs

Abstract In order to let device designers tune the short channel behavior of MOSFETs, a method is proposed in this work to demonstrate how to use LDD (lightly doped drain) and pocket implants to control RSCE (reverse short channel effect) and threshold voltage (Vt ) roll‐off. The method is based on the process parameters and silicon data of the 90 nm node technology of UMC (United Microelectronics Corporation). With the help of computers, 17 different process conditions of 8 different gate lengths were simulated using ISE TCAD to collect Vt variation data. Four characteristics representing the short channel behaviors of the MOSFETs were designed and extracted from the simulated data. Their empirical equations were also established subsequently. After verification, those mathematical models were demonstrated to help device designers in choosing the most suitable LDD and pocket implant parameters to generate required Vt characteristics.

Kink effect for 28 nm n–channel field–effect transistors after decoupled plasma nitridation treatment with annealing temperatures

The kink effect of drain leakage based on gated diode measurement metrology for the tested nMOSFETs with 28 nm HK/MG, gate–last and PDA or DPN nitridation processes was observed at VG around −0.6 V when the gate voltage was swept from −Vcc to 0.2 volt as VD = 0.1 V. Nevertheless, this interesting phenomenon was not evident as the gate voltage was reversely swept from 0.2 volt to -Vcc. The chief mechanism in speculation can be illustrated by the electrons coming from drain inducing capture–and–emission behaviour by the channel interface traps near the drain junction. While VG changes from −Vcc towards +0.2 V, interface states near valence band become lower than Fermi–level of silicon substrate. Electrons flow from drain to fill these interface states so that drive current (ID) increases. On the contrary, as VG changes from +0.2 V to −Vcc, the trapped electrons are recombined with holes from substrate so that ID is not affected. This kink effect for all of tested devices is not very distinct far and near. When the Poole–Frenkel (P–F) tunnelling electrons coming from gate to drain are evident in leakage, especially at the long–channel device, this effect will be probably counteracted, exhibited at the electrical characteristics of PDA group.

Effect of nitridation of hafnium silicate gate dielectric on positive bias temperature instability in pMOS devices

A detailed investigation of the effect of nitridation of hafnium silicate on positive bias temperature instability (PBTI) in n+-polySi gate pMOS capacitor structures has been presented. Our analysis shows that nitridation improves the intrinsic oxide breakdown field, reduces the equivalent oxide thickness (EOT) and as-grown surface state density Dit by an order of magnitude. On the other hand, like NBTI degradation, nitridation significantly enhances PBTI degradation in pMOS devices causing reduction in PBTI lifetime at a given applied voltage VG. However, both nitrided and non-nitrided gate stacks reaches 10 year lifetime at an applied gate bias of 1.2 V.

Characteristics and hot-carrier effects of strained pMOSFETs with SiGe channel and embedded SiGe source/drain stressors

The embedded SiGe source/drain stressor helpful to promote the drive current involves etching out the source/drain silicon and replacing it with SiGe filler. This process uses the lattice mismatch between silicon and germanium atoms making the silicon channel compressive. This compressive stress enhances hole mobility, and the pMOSFET performance can be enhanced. In this study, the characteristics of devices contained biaxial strain in channel and embedded SiGe source/drain stressor with different channel lengths and the channel hot carrier (CHC) in short channel pMOSFETs was explored, too.

Temperature dependence of substrate currents of MOSFETs under different drain and gate biases

In this study, the problem of substrate currents of metal-oxide-semiconductor field-effect transistors exhibiting different temperature dependence at different gate and drain voltages is investigated. The unsolved so-called ‘transition point’ problem is found to be ascribable to the different sensitivities of thermal kinetic energy and phonon scattering effects to the variation of drain voltages. To include the influence of temperature and gate voltage, a new mathematical model for substrate current is proposed, which also reveals that modeling using the lucky electron approach cannot obtain satisfactory accuracy and that the transverse electrical field from gate bias is not a negligible factor. With the evidence from experiments, this article also points out that using the substrate current to monitor the severity of the hot-carrier effect is not reliable when the drain voltage is lower than the transition point.