S.E. Kerns

Single-event charge enhancement in SOI devices

Studies are presented of single-particle ion effects in body-tied CMOS/silicon-on-insulator (SOI) devices. It is shown that two mechanisms can contribute to SOI soft-error rates: a direct ion-induced photocurrent and a local lateral bipolar current. The total amount of charge collected is sensitive to the relative locations of the ion strike and the body-to-source tie.<<ETX>>

Model for CMOS/SOI single-event vulnerability

A lumped-parameter model derived from transistor characterization data has been used in SPICE analyses to study and predict the single-event-upset thresholds for SIMOX SOI (separation by implantation of oxygen, silicon-on-insulator) SRAMs (static random-access memories) with a variety of cell designs. The modeling of CMOS/SOI transistors with fully bottomed sources and drains includes direct representation of the parasitic lateral bipolar structure. Results indicate that, in the SOI devices investigated, single events simulate a localized bipolar response, even in devices with bodies electrically tied to active nodes. The bipolar response enhances the destabilizing effect of an ion event. The total current impulse contributing to upset can be significantly greater than that produced by direct ionization within the hit transistor, i.e., devices can be upset by ions that deposit less than the total charge required to initiate logic state reversal. In light of this, advanced CMOS/SOI-SOS logic with short channel lengths (and therefore significant parasitic bipolar gain) may exhibit critical LETs (linear energy transfers) lower than expected from simple scaling rules, and thinning of the active regions may not significantly reduce single-event rates in such CMOS/SOI digital circuits. >

Effects of process parameter distributions and ion strike locations on SEU cross-section data (CMOS SRAMs)

The effect of statistical parameter distributions and stochastic ion strike locations in hardened memory arrays on observed SEU (single event upset) cross-section data is discussed. Application of numerical analysis to the parasitic bipolar gain distributions in SIMOX (separation by implantation of oxygen) SRAMs (static random-access memories) and the introduction of an effective critical charge based on sensitivities to ion strike locations explain the nonsaturating behavior of measured cross-section curves in SOI (silicon-on-insulator) and other hardened memories. A direct, analytical relationship between the measured cross-section curves seen in contemporary SOI CMOS SRAMs and the distribution of the parasitic bipolar beta values controlling each cell critical charge is presented. Results of this technique clearly indicate that distributed processing parameters and random ion strike locations lead to nonideal cross-section curves. The results also indicate that if the distribution for a critical parameter is known, the LET (linear energy transfer) threshold and shape of the upset cross-section curves can be anticipated. >

Simulation of SEU transients in CMOS ICs

An efficient computer simulation algorithm set, SITA, predicts the vulnerability of data stored in and processed by complex combinational logic circuits to SEU. SITA is described in detail to allow researchers to incorporate it into their error analysis packages. Required simulation algorithms are based on approximate closed-form equations modeling individual device behavior in CMOS logic units. Device-level simulation is used to estimate the probability that ion-device interactions produce erroneous signals capable of propagating to a latch (or an output node), and logic-level simulation to predict the spread of such erroneous, latched information through the IC. Simulation results are compared to those from SPICE for several circuit and logic configurations. SITA results are comparable to this established circuit-level code, and SITA can analyze circuits with state-of-the-art device densities (which SPICE cannot). At all IC complexity levels, SITA offers several factors of 10 savings in simulation time over SPICE. >

Photon generation by silicon diodes in avalanche breakdown

Light emission from a p-n diode biased in controlled avalanche breakdown has been measured over the photon energy range 1.4–3.4 eV. Previously published models are compared with measured data to associate specific mechanisms with avalanche photon emission in silicon. A multimechanism model fitting the measured spectrum is presented.

Single-event-induced charge collection and direct channel conduction in submicron MOSFETs

The single-event (SE) charge collection of an n-channel submicron MOSFET is described using three dimensional device simulations. Ion hits in the drain and in the channel region are considered. For submicron MOSFETs, we show simulation evidence that there may exist a direct source-drain conduction process induced by the ion, called ion-triggered channeling (ITC), which may be an important SE upset mechanism in deep submicron scaling. The further study of increased ion-track-length to device-gate-length ratios indicate that the direct source-drain conduction process assumes increased importance for increased scaling. >

SEU error rates in advanced digital CMOS

Single-event error rate analysis of radiation-hardened CMOS memory parts is presented. The statistical distribution on device processing parameters is shown to explain the non-ideal error cross-section data observed in contemporary six-transistor SRAMs designed for space-based operation. A procedure for evaluating the expected error rate for these parts is presented and applied to a typical data set. The method, which arises from a development of the upset rate convolution integral, can be applied in a generic fashion using conventional ground-based test data to provide a realistic upset-rate estimate for space flight conditions.<<ETX>>

Body tie placement in CMOS/SOI digital circuits for transient radiation environments

The authors present criteria for the use of body ties to reduce or eliminate parasitic bipolar effects important in the transient radiation response of SOI/CMOS devices. A theoretically derived body tie spacing rule is verified using both TRIGSPICE and PISCES II with photocurrent injection capabilities. The tie spacing rule, which is independent of feature size within bounds, provides a simple guideline for design/layout for CMOS/SOI digital circuits for harsh transient radiation environment. >

Comparative analysis of metal and optical interconnect technology

Barriers to industrial implementation of optical interconnects on an IC center on the balance between power requirements and speed improvements over existing metal interconnect systems. This paper focuses on such comparison based on empirically measured quantum efficiency and circuit-level projections. Multiple forms of clock distribution schemes are analyzed to show that the power requirements for optical interconnect are comparable to those of conventional metal interconnects. Implementing optical technology on long interconnect lines will improve the speed performance of ICs. The availability of such a method will allow design engineers to guide the partitioning of optical and conventional interconnects within ICs.

On the aging of avalanche light emission from silicon junctions

The evolution of photon emission from the emitter-base junctions of bipolar transistors during electrical aging is monitored for the first time. Both electrical and optical characteristics are analyzed. Local variations of light emission intensity are observed for junctions biased at avalanche breakdown. During aging, regions of emission coalesce into small, bright regions; the total emission for the entire junction remains stable and relatively high. Changes in transistor current gain and breakdown voltage correlate with changes in light emission, and are consistent with a hydrogen migration model.