Michael L. Alles

Charge Collection and Charge Sharing in a 130 nm CMOS Technology

Charge sharing between adjacent devices can lead to increased Single Event Upset (SEU) vulnerability. Key parameters affecting charge sharing are examined, and relative collected charge at the hit node and adjacent nodes are quantified. Results show that for a twin-well CMOS process, PMOS charge sharing can be effectively mitigated with the use of contacted guard-ring, whereas a combination of contacted guard-ring, nodal separation, and interdigitation is required to mitigate the NMOS charge sharing effect for the technology studied

The contribution of nuclear reactions to heavy ion single event upset cross-section measurements in a high-density SEU hardened SRAM

Heavy ion irradiation was simulated using a Geant4 based Monte-Carlo transport code. Electronic and nuclear physics were used to generate statistical profiles of charge deposition in the sensitive volume of an SEU hardened SRAM. Simulation results show that materials external to the sensitive volume can affect the experimentally measured cross-section curve.

HBD layout isolation techniques for multiple node charge collection mitigation

A three-dimensional (3D) technology computer-aided design (TCAD) model was used to simulate charge collection at multiple nodes. Guard contacts are shown to mitigate the charge collection and to more quickly restore the well potential, especially in PMOS devices. Mitigation of the shared charge collection in NMOS devices is accomplished through isolation of the P-wells using a triple-well option. These techniques have been partially validated through heavy-ion testing of three versions of flip-flop shift register chains.

A Bias-Dependent Single-Event Compact Model Implemented Into BSIM4 and a 90 nm CMOS Process Design Kit

A single-event model capable of capturing bias- dependent effects has been developed and integrated into the BSIM4 transistor model and a 90 nm CMOS process design kit. Simulation comparisons with mixed mode TCAD are presented.

Analysis of Parasitic PNP Bipolar Transistor Mitigation Using Well Contacts in 130 nm and 90 nm CMOS Technology

Three-dimensional TCAD models are used in mixed- mode simulations to analyze the effectiveness of well contacts at mitigating parasitic PNP bipolar conduction due to a direct hit ion strike. 130 nm and 90 nm technology are simulated. Results show careful well contact design can improve mitigation. However, well contact effectiveness is seen to decrease from the 130 nm to the 90 nm simulations.

Single-event charge enhancement in SOI devices

Studies are presented of single-particle ion effects in body-tied CMOS/silicon-on-insulator (SOI) devices. It is shown that two mechanisms can contribute to SOI soft-error rates: a direct ion-induced photocurrent and a local lateral bipolar current. The total amount of charge collected is sensitive to the relative locations of the ion strike and the body-to-source tie.<<ETX>>

Directional Sensitivity of Single Event Upsets in 90 nm CMOS Due to Charge Sharing

Heavy-ion testing of a radiation-hardened-by-design (RHBD) 90 nm dual interlocked cell (DICE latch) shows significant directional sensitivity results impacting observed cross-section and LET thresholds. 3-D TCAD simulations show this directional effect is due to charge sharing and parasitic bipolar effects due to n-well potential collapse.

Effect of Well and Substrate Potential Modulation on Single Event Pulse Shape in Deep Submicron CMOS

Simulations are used to characterize the single event transient current and voltage waveforms in deep submicron CMOS integrated circuits. Results indicate that the mechanism controlling the height and duration of the observed current plateau is the redistribution of the electrostatic potential in the substrate following a particle strike. Quantitative circuit and technology factors influencing the mechanism include restoring current, device sizing, and well and substrate doping.

Model for CMOS/SOI single-event vulnerability

A lumped-parameter model derived from transistor characterization data has been used in SPICE analyses to study and predict the single-event-upset thresholds for SIMOX SOI (separation by implantation of oxygen, silicon-on-insulator) SRAMs (static random-access memories) with a variety of cell designs. The modeling of CMOS/SOI transistors with fully bottomed sources and drains includes direct representation of the parasitic lateral bipolar structure. Results indicate that, in the SOI devices investigated, single events simulate a localized bipolar response, even in devices with bodies electrically tied to active nodes. The bipolar response enhances the destabilizing effect of an ion event. The total current impulse contributing to upset can be significantly greater than that produced by direct ionization within the hit transistor, i.e., devices can be upset by ions that deposit less than the total charge required to initiate logic state reversal. In light of this, advanced CMOS/SOI-SOS logic with short channel lengths (and therefore significant parasitic bipolar gain) may exhibit critical LETs (linear energy transfers) lower than expected from simple scaling rules, and thinning of the active regions may not significantly reduce single-event rates in such CMOS/SOI digital circuits. >

Two-dimensional methodology for modeling radiation-induced off-state leakage in CMOS technologies

A modeling approach using two-dimensional device simulations is presented, which enables the extraction of parameters for the radiation-induced parasitic MOSFET created at the edge of the shallow trench isolation (STI) oxide. With the model, one can estimate drain-to-source off-state leakage current (I/sub OFF/) resulting from build-up of oxide trapped charge (N/sub OT/). The impact of nonuniform N/sub OT/ build-up in the STI resulting from total ionizing dose (TID) exposure and external bias conditions is analyzed through volumetric simulations and compared to experimental data. Saturation for the off-state leakage current as a function of trapped charge is also investigated.