S.F. Feste

Threshold Voltage Variation in SOI Schottky-Barrier MOSFETs

The inhomogeneity of Schottky-barrier (SB) height Phi_B is found to strongly affect the threshold voltage V_th of SB-MOSFETs fabricated in ultrathin body silicon-on-insulator (SOI). The magnitude of this influence is dependent on gate oxide thickness t_OX and SOI body thickness; the contribution of inhomogeneity to the V_th variation becomes less pronounced with smaller t_OX and/or larger t_si . Moreover, an enhanced V_th variation is observed for devices with dopant segregation used for reduction of the effective Phi_B . Furthermore, a multigate structure is found to help suppress the V_th variation by improving carrier injection through reduction of its sensitivity to the Phi_B inhomogeneity. A new method for extraction of Phi_B from room temperature transfer characteristics is also presented.

Measurement of effective electron mass in biaxial tensile strained silicon on insulator

We present measurements of the effective electron mass in biaxial tensile strained silicon on insulator (SSOI) material with 1.2 GPa stress and in unstrained SOI. Hall-bar metal oxide semiconductor field effect transistors on 60 nm SSOI and SOI were fabricated and Shubnikov–de Haas oscillations in the temperature range of T=0.4–4 K for magnetic fields of B=0–10 T were measured. The effective electron mass in SSOI and SOI samples was determined as mt=(0.20±0.01)m0. This result is in excellent agreement with first-principles calculations of the effective electron mass in the presence of strain.

Formation of steep, low Schottky-barrier contacts by dopant segregation during nickel silicidation

We present a systematic analysis of arsenic dopant segregation during nickel silicide formation. The slopes and concentrations of the arsenic dopant profiles at the NiSi∕Si interface have been studied as a function of implantation energy, implantation dose, and NiSi thickness. Silicidation induced dopant segregation conserves the dopant slope at the silicide/silicon interface up to NiSi thicknesses of three times the as-implanted peak depth before degrading. Best slopes and highest dopant concentrations are obtained for low implantation energies and thin NiSi layers. We also demonstrate that the steepness of the dopant profile at the NiSi∕Si interface can be significantly improved through a two-step annealing process for NiSi formation. For As, 1keV, 1×1015cm−2, and a 17nm NiSi layer, a NiSi∕Si junction with a dopant slope of 3.2nm/decade has been obtained. An effective Schottky barrier of ΦSB=0.12eV was determined by low temperature measurements of Schottky diodes with 20nm NiSi formed by an optimized an...

Electrical characterization of strained and unstrained silicon nanowires with nickel silicide contacts

We present electrical characterization of nickel monosilicide (NiSi) contacts formed on strained and unstrained silicon nanowires (NWs), which were fabricated by top-down processing of initially As(+) implanted and activated strained and unstrained silicon-on-insulator (SOI) substrates. The resistivity of doped Si NWs and the contact resistivity of the NiSi to Si NW contacts are studied as functions of the As(+) ion implantation dose and the cross-sectional area of the wires. Strained silicon NWs show lower resistivity for all doping concentrations due to their enhanced electron mobility compared to the unstrained case. An increase in resistivity with decreasing cross section of the NWs was observed for all implantation doses. This is ascribed to the occurrence of dopant deactivation. Comparing the silicidation of uniaxially tensile strained and unstrained Si NWs shows no difference in silicidation speed and in contact resistivity between NiSi/Si NW. Contact resistivities as low as 1.2 x 10(-8) Omega cm(-2) were obtained for NiSi contacts to both strained and unstrained Si NWs. Compared to planar contacts, the NiSi/Si NW contact resistivity is two orders of magnitude lower.

Strained Silicon-On-Insulator - Fabrication and Characterization

SSOI substrates were successfully fabricated using He ion implantation and annealing to relax thin (< 500nm) SiGe buffer layers, bonding and layer transfer processes to realize strained-Si layers onto oxide layers. The reduced thickness of the SiGe buffer possess numerous advantages such as reduced process costs for epitaxy and for reclaim of the handle wafer if the layer splitting is initiated in the SiGe/Si interface. The electron mobilities in the fabricated SSOI layers were measured using transistors with different gate lengths. An electron mobility of ~530 cm /Vs was extracted, being much higher than in non-strained SOI substrates. Furthermore, an 80% drive current (IDSAT) improvement has been measured for long channel devices.

Atomic layer deposition of HfO2 and Al2O3 layers on 300 mm Si wafers for gate stack technology

In this study, the authors present results on the structural, chemical, and electrical characterization of HfO2 thin layers on 300 mm Si wafers. The layers were prepared by atomic layer deposition using a liquid delivery system technology for metal organic precursors, which allows an accurate control of the Hf precursor. After optimization of the deposition process with an alkylamide precursor for Hf and ozone chemistry, the growth of the SiOx interfacial layer between the HfO2 layer and the Si substrate could be minimized using TiN as metal gate. In addition, the authors studied the effect of Al2O3 interfacial layers on the properties of metal-oxide-semiconductor capacitor resulting in a positive flat band voltage shift of up to ∼300 mV according to the layer thickness. Gate stacks with equivalent oxide thicknesses around 1.1 nm showed leakage current densities as low as 1.1×10−2 A/cm2 at VFB of 1 V. In addition, the capacitance-voltage curves for thin HfO2 layers indicated a negligible hysteresis, below...

Hole mobilities and electrical characteristics of Ω- gated silicon nanowire array FETs with 〈110〉 - and 〈100〉 - channel orientation

We report on the fabrication and electrical characterization of Ω- gated nanowire (NW) array pFETs on SOI. Devices with gate lengths of L = 400nm and L = 2 µm and 〈110〉 - and 〈100〉 - channel orientations were fabricated using a top-down approach. Each device consists of up to 1500 NWs with a crosssection of 20×20nm². The devices feature excellent electrical characteristics with high on-currents, I<inf>on</inf>/I<inf>off</inf> ratio of 10⁸, close to ideal inverse sub-threshold slopes of 64 mV/dec and low series resistances of 200Ω. NW-array FETs aligned along the 〈110〉 - direction showed ×1.4 larger on-currents and ×1.3 higher transconductances compared to devices aligned along the 〈100〉 - direction. Hole mobilities in NW-array pFETs with 〈110〉 - and 〈100〉 - channel orientation were measured employing a split-CV technique. NW FETs aligned along a 〈110〉 - direction display a 40% higher hole mobility at low as well as at high vertical electric field compared to devices along the 〈100〉 - direction.

Performance enhancement of uniaxially-tensile strained Si NW-nFETs fabricated by lateral strain relaxation of SSOI

We present experimental results on mobility enhancement and on-current gain in Si NW-FETs fabricated on SOI and biaxially strained SOI. In SSOI long channel devices a 2.3 times larger mobility and similar on-current improvement compared to SOI are measured. Measurements on SSOI NW-FETs with different length to width ratio highlight that mobility enhancement due to lateral strain relaxation sensitively depends on the device geometry due to the size dependence of lateral strain relaxation. For maximum performance enhancement due to lateral strain relaxation SSOI devices must have a large length to width ratio. Furthermore, the geometry dependence of lateral strain relaxation to achieve uniaxial tensile strain is investigated with finite element simulations.

Strained and unstrained Si nanowire FETs

Recent experimental results on Si nanowire MOSFETs are presented. The devices were fabricated in a top-down approach on unstrained and biaxial strained SOI substrates exhibiting good I-V characteristics with Ion/Ioff-ratios of 107 and off-currents as low as 10{−-su13}A. Subthreshold slopes of about 70mV/dec for SOI n- and p-FETs and 65mV/dec for strained SOI n-FETs were obtained. The on-current and transconductance of Si NW-FETs fabricated on strained SOI substrates are 2.5 and 2.1 times larger, respectively, due to the uniaxial tensile strain along the wires. Moreover, current transport on surfaces with different crystal orientation in NWs is employed to match on-currents of SOI n- and p-FETs.

Large current enhancement in n-MOSFETs with strained Si on insulator

As scaling of the critical transistor dimensions below 65 nm has been slowed down, the implementation of novel materials, especially high mobility channel materials is most attractive to boost the transistor performance. Applying strain to silicon has become a successful route. The electron mobility can be enhanced by biaxial strain introduced into Si by epitaxial growth of Si on a strain relaxed SiGe layer or by so called process induced methods applied directly on transistor level. The combination of strained Si and SOI is particularly promising due to the combination of the enhanced mobilities and the inherent advantages of SOI. First long channel n-MOSFETs with gate lengths of 5 to 50 mum and a 6.6 nm thick SiO2 gate dielectric were fabricated. For comparison, devices on unstrained SOI were made. The transfer characteristics of a fully depleted sSOI-MOSFET with a gate length of 5 mum and a gate width of 20 mum indicating an inverse sub-threshold slope of 75mV/dec.