S. Habicht

Ultrathin Ni Silicides With Low Contact Resistance on Strained and Unstrained Silicon

Ultrathin Ni silicides were formed on silicon-on-insulator (SOI) and biaxially tensile strained SOI (SSOI) substrates. The Ni layer thickness crucially determines the silicide phase formation: With a 3-nm Ni layer, high-quality epitaxial NiSi2 layers were grown at temperatures > 450°C, while NiSi was formed with a 5-nm-thick Ni layer. A very thin Pt interlayer, to incorporate Pt into NiSi, improves the thermal stability and the interface roughness and lowers the contact resistivity. The contact resistivity of epitaxial NiSi2 is about one order of magnitude lower than that of a NiSi layer on both As- and B-doped SOI and SSOI.

Electrical characterization of strained and unstrained silicon nanowires with nickel silicide contacts

We present electrical characterization of nickel monosilicide (NiSi) contacts formed on strained and unstrained silicon nanowires (NWs), which were fabricated by top-down processing of initially As(+) implanted and activated strained and unstrained silicon-on-insulator (SOI) substrates. The resistivity of doped Si NWs and the contact resistivity of the NiSi to Si NW contacts are studied as functions of the As(+) ion implantation dose and the cross-sectional area of the wires. Strained silicon NWs show lower resistivity for all doping concentrations due to their enhanced electron mobility compared to the unstrained case. An increase in resistivity with decreasing cross section of the NWs was observed for all implantation doses. This is ascribed to the occurrence of dopant deactivation. Comparing the silicidation of uniaxially tensile strained and unstrained Si NWs shows no difference in silicidation speed and in contact resistivity between NiSi/Si NW. Contact resistivities as low as 1.2 x 10(-8) Omega cm(-2) were obtained for NiSi contacts to both strained and unstrained Si NWs. Compared to planar contacts, the NiSi/Si NW contact resistivity is two orders of magnitude lower.

Atomic layer deposition of HfO2 and Al2O3 layers on 300 mm Si wafers for gate stack technology

In this study, the authors present results on the structural, chemical, and electrical characterization of HfO2 thin layers on 300 mm Si wafers. The layers were prepared by atomic layer deposition using a liquid delivery system technology for metal organic precursors, which allows an accurate control of the Hf precursor. After optimization of the deposition process with an alkylamide precursor for Hf and ozone chemistry, the growth of the SiOx interfacial layer between the HfO2 layer and the Si substrate could be minimized using TiN as metal gate. In addition, the authors studied the effect of Al2O3 interfacial layers on the properties of metal-oxide-semiconductor capacitor resulting in a positive flat band voltage shift of up to ∼300 mV according to the layer thickness. Gate stacks with equivalent oxide thicknesses around 1.1 nm showed leakage current densities as low as 1.1×10−2 A/cm2 at VFB of 1 V. In addition, the capacitance-voltage curves for thin HfO2 layers indicated a negligible hysteresis, below...

Lanthanum Lutetium oxide integration in a gate-first process on SOI MOSFETs

The chemical reactions at the higher-k LaLuO<inf>3</inf>/Ti<inf>1</inf>N<inf>X</inf>/poly-Si gate stack interfaces are studied after high temperature treatment. A Ti-rich TiN metal layer degrades the gate stack performance after high temperature annealing. The gate stack containing TiN/LaLuO<inf>3</inf> with a near stoichiometric TiN layer is stable during 1000 °C, 5s anneals. Both electrical and structural characterization methods are employed to explore the thermal stability of the gate stack. Based on these results an integration of TiN/LaLuO<inf>3</inf> in a gatefirst MOSFET process on SOI is shown.

Hole mobilities and electrical characteristics of Ω- gated silicon nanowire array FETs with 〈110〉 - and 〈100〉 - channel orientation

We report on the fabrication and electrical characterization of Ω- gated nanowire (NW) array pFETs on SOI. Devices with gate lengths of L = 400nm and L = 2 µm and 〈110〉 - and 〈100〉 - channel orientations were fabricated using a top-down approach. Each device consists of up to 1500 NWs with a crosssection of 20×20nm². The devices feature excellent electrical characteristics with high on-currents, I<inf>on</inf>/I<inf>off</inf> ratio of 10⁸, close to ideal inverse sub-threshold slopes of 64 mV/dec and low series resistances of 200Ω. NW-array FETs aligned along the 〈110〉 - direction showed ×1.4 larger on-currents and ×1.3 higher transconductances compared to devices aligned along the 〈100〉 - direction. Hole mobilities in NW-array pFETs with 〈110〉 - and 〈100〉 - channel orientation were measured employing a split-CV technique. NW FETs aligned along a 〈110〉 - direction display a 40% higher hole mobility at low as well as at high vertical electric field compared to devices along the 〈100〉 - direction.

Performance enhancement of uniaxially-tensile strained Si NW-nFETs fabricated by lateral strain relaxation of SSOI

We present experimental results on mobility enhancement and on-current gain in Si NW-FETs fabricated on SOI and biaxially strained SOI. In SSOI long channel devices a 2.3 times larger mobility and similar on-current improvement compared to SOI are measured. Measurements on SSOI NW-FETs with different length to width ratio highlight that mobility enhancement due to lateral strain relaxation sensitively depends on the device geometry due to the size dependence of lateral strain relaxation. For maximum performance enhancement due to lateral strain relaxation SSOI devices must have a large length to width ratio. Furthermore, the geometry dependence of lateral strain relaxation to achieve uniaxial tensile strain is investigated with finite element simulations.

Formation and characterization of ultra-thin Ni silicides on strained and unstrained silicon

Ultra thin Ni-silicides were formed on silicon-on-insulator (SOI) and biaxially tensile strained Si-on-insulator (SSOI) substrates. Epitaxial NiSi<inf>2</inf> layers were formed with a 3 nm Ni layer at T>400°C, while a polycrystalline NiSi layer was with a 5nm thick Ni layer. The NiSi<inf>2</inf> layer quality advances with increasing temperature. A very thin Pt interlayer, to incorporate Pt into NiSi, forming Ni<inf>1-x</inf>Pt<inf>x</inf>Si, improves the thermal stability, the interface roughness and lowers the contact resistivity. The Schottky barrier heights (SBH) of these silicides were measured on n-Si(100). Ni<inf>1-x</inf>Pt<inf>x</inf>Si shows the highest SBH. The SBH of NiSi<inf>2</inf> layers decreases by improving the layer interface. Surprisingly, the contact resistivity of epitaxial NiSi<inf>2</inf> is about one order of magnitude lower than that of NiSi on both, As and B doped SOI and SSOI, The lowest value of 7×10⁻⁸ Ω cm² was measured on B doped SSOI.

Epitaxial growth of NiSi2 induced by sulfur segregation at the NiSi2/Si(100) interface

Epitaxial growth of a NiSi 2 layer was observed on S + ion-implanted Si(100) at a low temperature of 550 °C. Depending on the S + dose and the Ni thickness, we identified different nickel silicide phases. High quality and uniform epitaxial NiSi 2 layers formed at temperatures above 700 °C with a 20-nm Ni on high dose S + implanted Si(100), whereas no epitaxy was observed for a 36-nm Ni layer. We assume that the presence of sulfur at the silicide/Si(100) interface favors the nucleation of the NiSi 2 phase. The S atom distributions showed ultrasteep S depth profiles (3 nm/decade) in the silicon, which results from the snow-plow effect during silicidation and the segregation of S to the interface due to the low solubility of S in both Si and the silicide.

Strained and unstrained Si nanowire FETs

Recent experimental results on Si nanowire MOSFETs are presented. The devices were fabricated in a top-down approach on unstrained and biaxial strained SOI substrates exhibiting good I-V characteristics with Ion/Ioff-ratios of 107 and off-currents as low as 10{−-su13}A. Subthreshold slopes of about 70mV/dec for SOI n- and p-FETs and 65mV/dec for strained SOI n-FETs were obtained. The on-current and transconductance of Si NW-FETs fabricated on strained SOI substrates are 2.5 and 2.1 times larger, respectively, due to the uniaxial tensile strain along the wires. Moreover, current transport on surfaces with different crystal orientation in NWs is employed to match on-currents of SOI n- and p-FETs.

NiSi nano-contacts to strained and unstrained silicon nanowires

Nano-contacts of NiSi to n⁺ and p⁺ doped strained and unstrained Si nanowires (NWs) were studied. Several Ni silicide phases were found: Ni<inf>2</inf>Si formed under the Ni electrodes, Ni<inf>3</inf>Si very close to the Ni electrodes, while NiSi was observed along the Si NWs. The NiSi nanowire length decreases with increasing wire cross section A. The silicidation speed along the Si NW shows a linear relation to 1/A, indicating volume silicidation of the Si NW. Uniaxial strain seems to have no effect on the silicidation speed. Contact resistivities as low as 1.2×10⁻⁸ Ω·cm² were obtained for NiSi contacts to both, strained and unstrained Si nanowires.