S. Martinie

Soft-errors induced by terrestrial neutrons and natural alpha-particle emitters in advanced memory circuits at ground level

Abstract This review covers our recent (2005–2010) experiments and modeling-simulation work dedicated to the evaluation of natural radiation-induced soft errors in advanced static memory (SRAM) technologies. The impact on the chip soft-error rate (SER) of both terrestrial neutrons induced by cosmic rays and alpha-particle emitters, generated from traces of radioactive contaminants in CMOS process or packaging materials, has been experimentally investigated by life (i.e. real-time) testing performed at ground level on the Altitude Single-event Effect Test European Platform (ASTEP) and underground at the underground laboratory of modane (LSM). The paper describes these two test platforms and surveys the characterization results obtained for two SRAM technology nodes (130xa0nm and 65xa0nm). Experimental results concerning the characterization of the natural radiation environment are also reported.

Real-time Soft-Error testing of 40nm SRAMs

This work reports the real-time Soft-Error Rate (SER) characterization of more than 7 Gbit of SRAM circuits manufactured in 40 nm CMOS technology and subjected to natural radiation (atmospheric neutrons). This experiment has been conducted since March 2011 at mountain altitude (2552 m of elevation) on the ASTEP Platform. The first experimental results, cumulated over more than 7,500 h of operation, are analyzed in terms of single bit upset, multiple cell upsets, physical bitmap and convergence of the SER. The comparison of the experimental data with Monte Carlo simulations and accelerated tests is finally reported and discussed.

Further Insights in TFET Operation

Based on the band diagram analysis and systematic measurements, comprehensive description of the output characteristics of tunnel FETs (TFETs) operation is proposed. We show that both tunneling junctions have to be considered simultaneously to explain TFET behavior correctly. For the first time, we present and investigate in detail untruncated I_D(V_D) measurements of TFETs. We prove that competition between the two tunneling junctions explains these experiments. Insights on the links between I_D(V_G) and I_D(V_D) curves are provided, which reveal the origin of the tunneling current in the device. Our theory also enables to clarify previously reported I_D(V_D) results.

Underground Experiment and Modeling of Alpha Emitters Induced Soft-Error Rate in CMOS 65 nm SRAM

This work reports a long-duration

Analytical Modeling of Alpha-Particle Emission Rate at Wafer-Level

(sim {3}~{rm years})

First demonstration of strained SiGe nanowires TFETs with ION beyond 700µA/µm

real-time underground experiment of 65 nm SRAM technology at the underground laboratory of Modane (LSM) to quantify the impact of alpha-emitter on the Soft-Error Rate (SER). We developed an original and full analytical charge deposition based on non constant Linear Energy Transfer (LET) to accurately model the diffusion/collection approach. Monte Carlo simulation results based on this improved model have been compared to experimental data to analyze the impact of alpha-particle production inside the circuit silicon material for both single and multiple chip upsets. Finally, the respective contributions of alpha emitters and atmospheric neutrons to the circuit Soft-Error Rate (SER) are evaluated and compared, considering additional real-time measurements performed in altitude on the ASTEP platform.

Alpha-Particle Induced Soft-Error Rate in CMOS 130 nm SRAM

Alpha-particle emissivity at wafer-level has been analytically modeled for material layers contaminated by uranium and/or thorium impurities. Our approach evaluates the number (or the fraction) of escaping alpha particles from any monolayer or multilayer of arbitrary material composition. The global emissivity of the (stacked) material and its corresponding alpha-particle energy spectrum can be also analytically derived. The model has been fully validated with Monte Carlo simulation in terms of alpha-particle emissivity and energy spectra for different layer thicknesses and detection threshold energies. Finally, we propose a general nomogram for silicon material directly giving the alpha-particle emissivity versus the silicon contamination level expressed in ppb of uranium and thorium.

Leti-UTSOI2.1: A Compact Model for UTBB-FDSOI Technologies—Part II: DC and AC Model Description

We present for the first time high performance Nanowire (NW) Tunnel FETs (TFET) obtained with a CMOS-compatible process flow featuring compressively strained Si_1-xGe_x (x=0, 0.2, 0.25) nanowires, Si_0.7Ge_0.3 Source and Drain and High-K/Metal gate. Nanowire architecture strongly improves electrostatics, while low bandgap channel (SiGe) provides increased band-to-band tunnel (BTBT) current to tackle low ON current challenges. We analyse the impact of these improvements on TFETs and compare them to MOSFET ones. Nanowire width scaling effects on TFET devices are also investigated, showing a W^-3 dependence of ON current (I_ON) per wire. The fabricated devices exhibit higher I_ON than any previously reported TFET, with values up to 760μA/μm and average subthreshold slopes (SS) of less than 80mV/dec.

Detecting Unintended Schottky Junctions and Their Impact on Tunnel FET Characteristics

We report the modeling and simulation of the soft-error rate (SER) in CMOS 130 nm SRAM induced by alpha-particle emission in silicon due to uranium contamination at ppb concentration levels. Monte-Carlo simulation results have been confronted to experimental data obtained from long-duration (>;20 000 h) real-time measurements performed at the under-ground laboratory of Modane (LSM) and from experimental counting characterization using an ultra low background alpha-particle gas proportional counter. The calibration of simulations with the measured SER allowed us to determine a 238U contamination level of 0.37 ppb (considered at secular equilibrium) in very good agreement with both corresponding alpha-particle emissivity levels measured and simulated at wafer-level in the range 1.1 to 2.3 × 10-3 alpha/cm2/h.

Underground characterization and modeling of alpha-particle induced Soft-Error Rate in CMOS 65nm SRAM

A detailed presentation of the latest version of Leti-UTSOI compact model is provided. Leti-UTSOI2 is the first available model able to describe the behavior of ultrathin body and BOX fully depleted silicon-on-insulator transistors in all bias configurations, including strong forward back bias. In this paper, compact modeling of intrinsic currents and charges, including all physical effects required to describe decananometer transistors, is detailed. This model is valid for all independent double-gate architectures, very accurate and feature excellent predictability over technological parameters.