S. Uznanski

Real-time Soft-Error testing of 40nm SRAMs

This work reports the real-time Soft-Error Rate (SER) characterization of more than 7 Gbit of SRAM circuits manufactured in 40 nm CMOS technology and subjected to natural radiation (atmospheric neutrons). This experiment has been conducted since March 2011 at mountain altitude (2552 m of elevation) on the ASTEP Platform. The first experimental results, cumulated over more than 7,500 h of operation, are analyzed in terms of single bit upset, multiple cell upsets, physical bitmap and convergence of the SER. The comparison of the experimental data with Monte Carlo simulations and accelerated tests is finally reported and discussed.

Underground Experiment and Modeling of Alpha Emitters Induced Soft-Error Rate in CMOS 65 nm SRAM

This work reports a long-duration

Alpha-Particle Induced Soft-Error Rate in CMOS 130 nm SRAM

(\sim {3}~{\rm years})

Experimental characterization of process corners effect on SRAM alpha and neutron Soft Error Rates

real-time underground experiment of 65 nm SRAM technology at the underground laboratory of Modane (LSM) to quantify the impact of alpha-emitter on the Soft-Error Rate (SER). We developed an original and full analytical charge deposition based on non constant Linear Energy Transfer (LET) to accurately model the diffusion/collection approach. Monte Carlo simulation results based on this improved model have been compared to experimental data to analyze the impact of alpha-particle production inside the circuit silicon material for both single and multiple chip upsets. Finally, the respective contributions of alpha emitters and atmospheric neutrons to the circuit Soft-Error Rate (SER) are evaluated and compared, considering additional real-time measurements performed in altitude on the ASTEP platform.

Monte-Carlo Based Charge Sharing Investigations on a Bulk 65 nm RHBD Flip-Flop

We report the modeling and simulation of the soft-error rate (SER) in CMOS 130 nm SRAM induced by alpha-particle emission in silicon due to uranium contamination at ppb concentration levels. Monte-Carlo simulation results have been confronted to experimental data obtained from long-duration (>;20 000 h) real-time measurements performed at the under-ground laboratory of Modane (LSM) and from experimental counting characterization using an ultra low background alpha-particle gas proportional counter. The calibration of simulations with the measured SER allowed us to determine a 238U contamination level of 0.37 ppb (considered at secular equilibrium) in very good agreement with both corresponding alpha-particle emissivity levels measured and simulated at wafer-level in the range 1.1 to 2.3 × 10-3 alpha/cm2/h.

SEE test and modeling results on 45nm SRAMs with different well strategies

This paper shows alpha and neutron experimental Soft Error Rate characterization of a SRAM test vehicle processed with different process corners in order to emulate the variability encountered in volume production. It allows assessing large variability effects with few samples that are compatible with accelerated SER testing. This allows investigating the effect of variability in mass-production on soft error rate of deca-nanometric technologies.

A GPU/CUDA implementation of the collection-diffusion model to compute SER of large area and complex circuits

Charge sharing in a dual-interlocked storage cell (DICE) Flip-Flop (FF) manufactured in 65 nm CMOS Bulk is analyzed using a new proprietary Monte-Carlo tool suite named TIARA (Tool suIte for rAdiation Reliability Assessment). Monte-Carlo simulations show the simultaneous charge collection by transistors in the same well is 5 X more important than charge sharing in different wells. Additionally, TIARA simulations are used to identify layout weaknesses. Subsequent layout modifications have increased the threshold LET by 50%.

Underground characterization and modeling of alpha-particle induced Soft-Error Rate in CMOS 65nm SRAM

This paper presents heavy ion experimental results on SRAMs processed with 45nm bulk technology. Experiments were analyzed for Multiple Cells Upset (MCU) occurrence. The tested device was especially designed for MCU studies. In order to limit their spread it embeds different well strategies: usage of triple well layer and several densities of well ties.

Alpha-emitter induced soft-errors in CMOS 130nm SRAM: Real-time underground experiment and Monte-Carlo simulation

This work reports the CUDA implementation of the collection-diffusion model to compute the soft-error rate (SER) of large area and/or complex circuits on graphics processing units (GPU). We detail the time parallelization introduced in the algorithm to accelerate by one order of magnitude the SER calculation. Code performances are evaluated on a NVIDIA Tesla C1060 GPU card for the calculation of the SER of a 65nm SRAM circuit subjected to an alpha-particle source irradiation.

Single Event Upset and Multiple Cell Upset Modeling in Commercial Bulk 65-nm CMOS SRAMs and Flip-Flops

This work reports a long-duration (∼ 3 years) real-time underground experiment of 65 nm SRAM technology at the underground laboratory of Modane (LSM) to quantify the impact of alpha-emitter on Soft Error Rate. We developed an original and full analytical charge deposition based on non constant Linear Energy Transfer (LET) to accurately model the diffusion/collection approach. Monte-Carlo simulation results based on this new model have been confronted to experimental data to analyze the alpha-particles impact on Multiple Ship Upset.