S. Milosavljevic

Improved RF Devices for Future Adaptive Wireless Systems Using Two-Sided Contacting and AlN Cooling

This paper reviews special RF/microwave silicon device implementations in a process that allows two-sided contacting of the devices: the back-wafer contacted silicon-on-glass (SOG) substrate-transfer technology (STT) developed at DIMES. In this technology, metal transmission lines can be placed on the low-loss glass substrate, while the resistive/capacitive parasitics of the silicon devices can be minimized by a direct two-sided contacting. Focus is placed here on the improved device performance that can be achieved. In particular, high-quality SOG varactors have been developed and an overview is given of a number of innovative highly-linear circuit configurations that have successfully made use of the special device properties. A high flexibility in device design is achieved by two-sided contacting because it eliminates the need for buried layers. This aspect has enabled the implementation of varactors with special Ndx -2 doping profiles and a straightforward integration of complementary bipolar devices. For the latter, the integration of AlN heatspreaders has been essential for achieving effective circuit cooling. Moreover, the use of Schottky collector contacts is highlighted also with respect to the potential benefits for the speed of SiGe heterojunction bipolar transistors (HBTs).

High-Efficiency Silicon Photodiode Detector for Sub-keV Electron Microscopy

A silicon photodiode detector is presented for use in scanning electron microscopy (SEM). Enhanced imaging capabilities are achieved for sub-keV electron energy values by employing a pure boron (PureB) layer photodiode technology to deposit nanometer-thin photosensitive anodes. As a result, imaging using backscattered electrons is demonstrated for 50-eV electron landing energy values. The detector is built up of several closely packed photodiodes, and to obtain high scanning speed, each photodiode is engineered with low series resistance and low capacitance values. The low capacitance (<; 3 pF/mm2) is facilitated by thick, almost intrinsically-doped epitaxial layers grown to achieve the necessarily wide depletion regions. For the low series resistance, diode metallization has been patterned into a conductive grid directly on top of the nanometer-thin PureB-layer front-entrance window. Finally, a through-wafer aperture in the middle of the detector is micromachined for flexible positioning in the SEM system.

Versatile silicon photodiode detector technology for scanning electron microscopy with high-efficiency sub-5 keV electron detection

A new silicon electron detector technology for Scanning Electron Microscopy, based on ultrashallow p+n boron-layer photodiodes, features nm-thin anodes enabling low-energy electron detection with record-high sensitivity down to 200 eV. Designs with segmented, closely-packed photodiodes and through-wafer apertures allow flexible configurations for optimal material and/or topographical contrasts. A high scanning speed is obtained by growing a well-controlled, lightly-doped, tens-of-microns-thick epi-layer for low capacitance, and by patterning a conductive grid directly on the photosensitive surface for low series resistance.

Pure-boron chemical-vapor-deposited layers: A new material for silicon device processing

This paper places focus on the special properties of pure boron chemical-vapor deposition (CVD) thin-film layers that, in several device applications, have recently been shown to augment the potentials of silicon device integration. Besides forming a reliable an efficient dopant source for both ultrashallow and deep p+n junctions, the deposited amorphous boron (α-B) layer itself, even for sub-nm thicknesses, is instrumental in suppressing minority electron injection from the n-region into the p+ contact. Therefore, even for nm-shallow junctions where the current levels mainly will approach high Schottky-like values, the diodes exhibit saturation current levels that can become as low as that of conventional deep junctions. Moreover, the α-B layer has chemical etch properties that make it particularly suitable for integration as the front-entrance window in photodiodes for detecting nm-low-penetration-depth radiation and charged particles.

Ring-gate MOSFET test structures for measuring surface-charge-layer sheet resistance on high-resistivity-silicon substrates

Ring-gate MOSFET test structures have been developed with which a differential measurement technique can be used to accurately determine the surface-charge-layer sheet resistance on high-resistivity-silicon substrates. The difference in substrate properties and influence of special surface passivation techniques that are designed to suppress the otherwise conductive surface channel can thus be monitored and characterized for RF transmission line applications.

Special RF/microwave devices in Silicon-on-Glass Technology

This paper reviews special RF/microwave silicon device implementations in the back-wafer contacted Silicon-On-Glass (SOG) Substrate-Transfer Technology (STT) developed at DIMES. In this technology, metal transmission lines can be placed on the low-loss glass substrate, while the resistive/capacitive parasitics of the silicon devices can be minimized by a direct two-sided contacting. Focus is placed here on the device level aspects of the SOG process. In particular, complementary bipolar device integration and high-quality varactors for high-linearity adaptive circuits are treated in relationship to developments in back-wafer contacting and the integration of AlN heatspreaders.

Silicon-on-glass technology for RF and microwave device fabrication

This paper reviews the applications and potentials of back-wafer contacted silicon-on-glass (SOG) substrate-transfer technology (STT) particularly for RF and microwave silicon-device-design enhancement. This type of SOG process gives direct access to the part of the device that is usually connected via the bulk Si, by allowing advanced patterning and contacting of the backside of the wafer (back-wafer) with respect to the front of the wafer (front-wafer). In this manner the resistive and capacitive parasitics of the device itself, which in silicon often inhibit high-frequency (HF) performance, can be reduced to a minimum. At the same time new device concepts are made possible. Examples of fabricated devices (varactor diodes, vertical double-diffused MOSFETs (VDMOSFETs) and complementary bipolar transistors) are given and described in relationship to issues such as the very limited thermal budget permitted in the back-wafer processing and the inherently high thermal resistance of the SOG devices

Integration of laser-annealed junctions in a low-temperature high-k metal-gate MISFET

Integration and properties of devices processed by excimer laser annealing are presented. The best results are achieved by shallow implantations into a native-oxide-free silicon surface and laser annealing with the remainder of the device protected by an Al reflective layer. Low-temperature MISFETs are fabricated with a metal-gate high-k gate stack of PECVD SiO2 and ALD Al2O3 with an EOT of 9.2 nm and an Al-gate. The source/drain regions are self-aligned to the metal gate, which also serves as a laser masking reflective layer. Ablation of the masking layer is prevented due to the low thermal resistance of the thin underlying gate dielectric. The measured devices exhibit good current drivability, which improves with higher laser energy. The maximum processing temperature of the presented MISFETs is 400°C and can potentially to be reduced down to 300°C.

Deep p + junctions formed by drive-in from pure boron depositions

This paper presents a new method of supplying the high doses of boron needed for creating several micron deep p+n junctions. Chemical vapor deposition (CVD), in a Si/SiGe epitaxial reactor, of nanometer-thick pure boron layers is used to fabricate 5 μm deep p+n junctions. The 10 min B deposition is combined with a 195 min drive-in at 1100°C to give a resulting sheet resistance of 3.1 Ω/sq. For as-deposited B-layers in windows through an silicon dioxide isolation to the Si substrate, reactions of the Si with oxide at the perimeter of the deposited windows will be enhanced by the presence of the B-layer during the high-temperature drive-in. Detrimental effects such as lateral contact window widening, small surface defects and/or large spikes formation, are avoided by capping the surface of the windows with either thermal oxide in a selective process or a low-pressure CVD (LPCVD) oxide during the drive-in. A good electrical quality of the oxide capping layer was achieved. The surface morphology was investigated by atomic force and scanning electron microscopy (AFM/SEM) analysis and found to depend on the overall method of fabrication.

Ultra-low-temperature process modules for back-wafer-contacted silicon-on-glass RF/microwave technology

This paper reviews several novel process modules developed for the processing of the backside of the wafer of our substrate-transfer technology called back-wafer-contacted silicon-on-glass (SOG), which is in use for fabricating RF/microwave devices such as high-quality varactors and bipolar transistors. In this technology the silicon wafer is transferred to glass by gluing. The integrity of the acrylic adhesive limits the subsequent processing temperatures to less than 300°C. Ultra-low-temperature process modules have therefore been developed to nevertheless allow the creation of low-ohmic contacts and high-quality ultrashallow junctions. Moreover, a physical-vapor deposition of AlN provides an effective means of integrating a thin-film dielectric heatspreader.