E.J.G. Goudena

DIMES-01, a baseline BIFET process for smart sensor experimentation

Abstract The DIMES-01 BIFET baseline process is presented. The process and devices are described in relationship to their application in integrated silicon sensor research and development. In particular, the possibilities of introducing special sensor process modules and steps are treated.

Optimization of fully-implanted NPNs for high-frequency operation

With a very straightforward (low-cost) process flow as basis, fully-implanted washed-emitter-base (WEB) NPNs have been optimized for operation in the 10-30 GHz range. Above 20 GHz the best overall performance is achieved by heavy doping of the epi. A low-stress silicon rich nitride layer is proven effective as surface isolation before contact window dip-etch.

Improved RF Devices for Future Adaptive Wireless Systems Using Two-Sided Contacting and AlN Cooling

This paper reviews special RF/microwave silicon device implementations in a process that allows two-sided contacting of the devices: the back-wafer contacted silicon-on-glass (SOG) substrate-transfer technology (STT) developed at DIMES. In this technology, metal transmission lines can be placed on the low-loss glass substrate, while the resistive/capacitive parasitics of the silicon devices can be minimized by a direct two-sided contacting. Focus is placed here on the improved device performance that can be achieved. In particular, high-quality SOG varactors have been developed and an overview is given of a number of innovative highly-linear circuit configurations that have successfully made use of the special device properties. A high flexibility in device design is achieved by two-sided contacting because it eliminates the need for buried layers. This aspect has enabled the implementation of varactors with special Ndx -2 doping profiles and a straightforward integration of complementary bipolar devices. For the latter, the integration of AlN heatspreaders has been essential for achieving effective circuit cooling. Moreover, the use of Schottky collector contacts is highlighted also with respect to the potential benefits for the speed of SiGe heterojunction bipolar transistors (HBTs).

Sub-500/spl deg/C solid-phase epitaxy of ultra-abrupt p/sup +/-silicon elevated contacts and diodes

A well-controlled low-temperature process, demonstrated from 350/spl deg/C to 500/spl deg/C, has been developed for epitaxially growing elevated contacts and near-ideal diode junctions of Al-doped Si in contact windows to the Si substrate. A physical-vapor-deposited (PVD) amorphous silicon layer is converted to monocrystalline silicon selectively in the contact windows by using a PVD aluminum layer as a transport medium. This is a solid-phase-epitaxy (SPE) process by which the grown Si is Al-doped to at least 10/sup 18/ cm/sup -3/. Contact resistivity below 10/sup -7/ /spl Omega//spl middot/cm/sup 2/ is achieved to both p/sup -/ and p/sup +/ bulk-silicon regions. The elevated contacts have also been employed to fabricate p/sup +/-n diodes and p/sup +/-n-p bipolar transistors, the electrical characterization of which indicates a practically defect-free epitaxy at the interface.

Design and fabrication of infrared detector arrays for satellite attitude control

Abstract This paper describes the design, modelling and fabrication of infrared detectors for attitude control systems (ACS) for satellites. After a short introduction on the use and control of satellites in general, we explain the advantages of our integrated arrays of infrared detector units (pixels). Two types of detectors have been manufactured, a staggered array (ISA) with 32 pixels (in two staggered arrays of 16 pixels each) or in a cross of four staggered arrays (FPA) having 128 pixels in total. The choice depends upon the specific application (geostationairy or GEO orbit or low-altitude orbit). The detectors are based on a bipolar silicon process for the mechanical structure (electrochemically controlled etching (ECE)-KOH etching), with a SiN membrane for thermal isolation of the pixels, which have a polymer black coating for transduction of radiation to heat and n-type vs. p-type polysilicon thermopiles for heat detection. The pixel pitch is 600 μm, the black area is about 495×440 μm and the pixel sensitivity is about 55 V/W, at a thermopile resistance of 23.5 kΩ. The ISA measures in its present form 13.5×4 mm, the FPA measures 20.5×20.5 mm.

Special RF/microwave devices in Silicon-on-Glass Technology

This paper reviews special RF/microwave silicon device implementations in the back-wafer contacted Silicon-On-Glass (SOG) Substrate-Transfer Technology (STT) developed at DIMES. In this technology, metal transmission lines can be placed on the low-loss glass substrate, while the resistive/capacitive parasitics of the silicon devices can be minimized by a direct two-sided contacting. Focus is placed here on the device level aspects of the SOG process. In particular, complementary bipolar device integration and high-quality varactors for high-linearity adaptive circuits are treated in relationship to developments in back-wafer contacting and the integration of AlN heatspreaders.

Silicon-on-glass technology for RF and microwave device fabrication

This paper reviews the applications and potentials of back-wafer contacted silicon-on-glass (SOG) substrate-transfer technology (STT) particularly for RF and microwave silicon-device-design enhancement. This type of SOG process gives direct access to the part of the device that is usually connected via the bulk Si, by allowing advanced patterning and contacting of the backside of the wafer (back-wafer) with respect to the front of the wafer (front-wafer). In this manner the resistive and capacitive parasitics of the device itself, which in silicon often inhibit high-frequency (HF) performance, can be reduced to a minimum. At the same time new device concepts are made possible. Examples of fabricated devices (varactor diodes, vertical double-diffused MOSFETs (VDMOSFETs) and complementary bipolar transistors) are given and described in relationship to issues such as the very limited thermal budget permitted in the back-wafer processing and the inherently high thermal resistance of the SOG devices

Ultra-low-temperature process modules for back-wafer-contacted silicon-on-glass RF/microwave technology

This paper reviews several novel process modules developed for the processing of the backside of the wafer of our substrate-transfer technology called back-wafer-contacted silicon-on-glass (SOG), which is in use for fabricating RF/microwave devices such as high-quality varactors and bipolar transistors. In this technology the silicon wafer is transferred to glass by gluing. The integrity of the acrylic adhesive limits the subsequent processing temperatures to less than 300°C. Ultra-low-temperature process modules have therefore been developed to nevertheless allow the creation of low-ohmic contacts and high-quality ultrashallow junctions. Moreover, a physical-vapor deposition of AlN provides an effective means of integrating a thin-film dielectric heatspreader.

RF/microwave device fabrication in silicon-on-glass technology

This paper reviews recent developments in circuit and device implementations based on back-wafer contacted silicon-on-glass (SOG) substrate-transfer technology (STT). This technology has been specifically developed for the enhancement of silicon RF and microwave device and circuit performance. While metal transmission lines can be placed on the low-loss glass substrate, the resistive and capacitive parasitics of the silicon devices can also be minimized by a direct contacting of the parts of the devices that are usually connected via the bulk Si. Focus is placed here on the device level aspects of the SOG process, in particular high-quality varactors for high-linearity adaptive circuits and complementary bipolar device integration are treated in relationship to new developments in back-wafer contacting and the integration of AlN heatspreaders.

Low-Temperature Solid-Phase Epitaxy of Defect-Free Aluminum p + -doped Silicon for Nanoscale Device Applications

A solid phase epitaxy (SPE) technique was developed to grow p + aluminum-doped crystalline Si in a fully CMOS compatible process. This paper describes the experimental conditions leading to the selective growth of nanoscale single crystals where the location and dimensions are well controlled, even in the sub-100 nm range. The SPE Si crystals are defined by conventional lithography and show excellent electrical characteristics. Fifty-nanometer-thick p + SPE Si crystals were used to fabricate p + -n-p bipolar junction transistors. The remarkable control of the whole process, even in the sub-100 nm range, make this module directly usable for Si-based nanodevices.