Sabar D. Hutagalung

The effect of different dopant site (Cu and Ca) by magnesium on CaCu3Ti4O12 dielectric properties

CaCu3Ti4O12 (CCTO) is known as a material that possesses high dielectric constant (εrxa0~xa0104) and can be the best candidate to be used in electronic components that can be operated at low and high frequency. Unfortunately, high dielectric loss of CCTO can be the main obstacle for this material to be commercialized. In this paper, Mg was used as dopant into CCTO ceramics in order to reduce dielectric loss of CCTO and the dielectric properties of CCTO samples were characterized at high frequency (1xa0MHz–1xa0GHz). The samples were prepared via solid state method. Mg was used as dopant at different site of CCTO (Cu and Ca sites). All mixed powders were calcined at 900xa0°C for 12xa0h and subsequently sintered at 1030xa0°C for 10xa0h. X-ray diffractometer analysis proved the formation of complete single phase CCTO for all sintered samples. Scanning electron microscopy analysis showed the grain size became larger with the addition of dopant concentration. Enhanced dielectric constant was observed for most of the doped samples with most of the CaCu3−xMgxTi4O12 (Mg doped at Cu site) samples had higher dielectric constant and lower dielectric loss at frequency 1xa0MHz whereas the Ca1−xMgxCu3Ti4O12 (Mg doped at Ca site) samples exhibited higher dielectric constant and lower dielectric loss compared to the CaCu3−xMgxTi4O12 samples at 1xa0GHz. Thus, Mg replacement on Cu and Ca sites in CCTO gave a great influence on dielectric properties.

Optical and Electrical Characteristics of Silicon Nanowires Prepared by Electroless Etching

Silicon nanowires (SiNWs) were fabricated by the electroless etching of an n-type Si (100) wafer in HF/AgNO3. Vertically aligned and high-density SiNWs are formed on the Si substrates. Various shapes of SiNWs are observed, including round, rectangular, and triangular. The recorded maximum reflectance of the SiNWs is approximately 19.2%, which is much lower than that of the Si substrate (65.1%). The minimum reflectance of the SiNWs is approximately 3.5% in the near UV region and 9.8% in the visible to near IR regions. The calculated band gap energy of the SiNWs is found to be slightly higher than that of the Si substrate. The I–V characteristics of a freestanding SiNW show a linear ohmic behavior for a forward bias up to 2.0xa0V. The average resistivity of a SiNW is approximately 33.94xa0Ωxa0cm.

Study of the side gate junctionless transistor in accumulation region

Purpose n n n n nThe purpose of this paper is to analyse the operation of p-type side gate junctionless silicon transistor (SGJLT) in accumulation region through experimental measurements and 3-D TCAD simulation results. The variation of electric field components, carrier’s concentration and valence band edge energy towards the accumulation region is explored with the aim of finding the origin of SGJLT performance in the accumulation operational condition. n n n n nDesign/methodology/approach n n n n nThe device is fabricated by atomic force microscopy nanolithography on silicon-on-insulator wafer. The output and transfer characteristics of the device are obtained using 3-D Technology Computer Aided Design (TCAD) Sentaurus software and compared with experimental measurement results. The advantages of AFM nanolithography in contact mode and Silicon on Insulator (SOI) technology were implemented to fabricate a simple structure which exhibits the behaviour of field effect transistors. The device has 200-nm channel length, 100-nm gate gap and 4 μm for the distance between the source and drain contacts. The characteristics of the fabricated device were measured using an Agilent HP4156C semiconductor parameter analyzer (SPA). A 3-D TCAD Sentaurus tool is used as the simulation platform. The Boltzmann statistics is adopted because of the low doping concentration of the channel. Hydrodynamic model is taken to be as the main transport model for all simulations, and the quantum mechanical effects are ignored. A doping dependent Masetti mobility model was also included as well as an electric field dependent model with Shockley–Read–Hall (SRH) carrier recombination/generation. n n n n nFindings n n n n nWe have obtained that the device is a normally on state device mainly because of the lack of work functional difference between the gate and the channel. Analysis of electric field components’ variation, carrier’s concentration and valence band edge energy reveals that increasing the negative gate voltage drives the device into accumulation region; however, it is unable to increase the drain current significantly. The positive slope of the hole quasi-Fermi level in the accumulation region presents mechanism of carriers’ movement from source to drain. The influence of electric field because of drain and gate voltage on charge distribution explains a low increasing of the drain current when the device operates in accumulation regime. n n n n nOriginality/value n n n n nThe proposed side gate junctionless transistors simplify the fabrication process, because of the lack of gate oxide and physical junctions, and implement the atomic force microscopy nanolithography for fabrication process. The optimized structure with lower gap between gate and channel and narrower channel would present the output characteristics near the ideal transistors for next generation of scaled-down devices in both accumulation and depletion region. The presented findings are verified through experimental measurements and simulation results.

Dependency of electrical characteristics on nano gap variation in pinch off lateral gate transistors

The variation of electrical characteristics with nano size air gap variation between gates and channel of a pinch off lateral gate transistor were investigated using 3D Technology Computer Aided Design. It is found that smaller nanosize gaps which can be formed by approaching the lateral gates to the channel can improve the switching performance of the device significantly. Devices with different air gap demonstrate same on state current and maximum transconductance of 0.05 μS, however the on/off current ratio (ION/IOFF) is varied by three orders of magnitude. The parameters such as electric field and band energy variation are investigated in order to explain the variation of electrical characteristics by air gap variation.

Atomic force microscope base nanolithography for reproducible micro and nanofabrication

Atomic force microscopy nanolithography (AFM) is a strong fabrication method for micro and nano structure due to its high spatial resolution and positioning abilities. Mixing AFM nanolithography with advantage of silicon-on-insulator (SOI) technology provides the opportunity to achieve more reliable Si nanostructures. In this letter, we try to investigate the reproducibility of AFM base nanolithography for fabrication of the micro/nano structures. In this matter local anodic oxidation (LAO) procedure applied to pattern a silicon nanostructure on p-type (1015 cm-3) SOI using AFM base nanolithography. Then chemical etching is applied, as potassium hydroxide (saturated with isopropyl alcohol) and hydrofluoric etching for removing of Si and oxide layer, respectively. All parameters contributed in fabrication process were optimized and the final results revealed a good potential for using AFM base nanolithography in order to get a reproducible method of fabrication.

La‐Doped CaCu3Ti4O12 Prepared By Conventional And Microwave Processing

Two processing techniques were used to prepare separate samples of undoped and La‐doped CaCu3Ti4O12: the conventional furnace and microwave processing. Stoichiometric composition of undoped CaCu3Ti4O12 was produced by mixing starting materials of Ca(OH)2, CuO and TiO2 powder. The mixed powder was milled and then calcined, compacted and sintered using either a furnace (conventional) or a domestic microwave oven (microwave processing). The La2O3 was added to undoped CaCu3Ti4O12 in order to prepare the La‐doped CaCu3Ti4O12 with different doping concentrations. The conventional furnace heating technique requires a calcination temperature of 900°u2009C for 12 hours before the mixture is sintered at 1000°u2009C for 12 hours. However, a single phase CaCu3Ti4O12 compound was successfully synthesized using a microwave oven for a calcination time of 30 minutes. Longer microwave sintering time tends to produce denser CaCu3Ti4O12 pellets.