Prasun Ghosal

A heuristic method for constructing hexagonal Steiner minimal trees for routing in VLSI

In deep sub-micron regime, interconnect delays dominate VLSI circuit design. Thus, construction of cost-effective global routing trees is key to such designs. In order to reduce the interconnect delay, traditional Manhattan (M-) routing architectures are currently being replaced by the diagonal X architectures. A recent routing architecture is based on Y interconnects, involving the pervasive use of 0deg, 60deg, and 120deg oriented global and semi-global wirings. Unlike the X-routing, Y-routing Is observed to support regular routing grid, which as important for simplifying manufacturing processes and routing and design rule checking algorithms. In this paper, we propose a novel Y-routing algorithm which can solve reasonably sized problems in nominal time. The proposed method is capable of finding routing solutions for problem instances which could not be solved in reasonable time by some recently reported methods. Moreover, it can be easily extended for routing with any uniform orientation

Modeling and Analysis of Crosstalk Induced Effects in Multiwalled Carbon Nanotube Bundle Interconnects: An ABCD Parameter-Based Approach

In this paper, the crosstalk effects in both small and large diameter multiwalled carbon nanotube bundle interconnects (MWCNTs) for the future nanoscale integrated circuits are studied with the help of ABCD parameter matrix approach for global levels of interconnects at 22- and 14-nm technology nodes. Here, isolated MWCNTs are modeled using an equivalent single conductor transmission line. The simulation results show that the results are at par with the result of SPICE model. It is observed that performance wise, the large diameter MWCNT bundles are better than both small diameter MWCNT bundles and copper wire for both repeated and unrepeated interconnects. The same trend is observed with the number of inserted repeaters. For repeated wires, the optimized placement of repeaters offsets the delay advantage numbers of MWCNT bundles over copper wire. Technology scaling adversely impacts the delay advantage numbers of small diameter MWCNT bundles. As far as the worst-case crosstalk noise peak voltage is concerned, the large diameter MWCNT bundles also outperform both small diameter MWCNT bundles and copper wire for longer interconnects. However, for shorter interconnects, copper wire and small diameter bundles outclass the large diameter bundles due to their relatively larger time constant. We have compared our crosstalk analysis results with the earlier work to justify the validity of our proposed model and observed that the results with our model are in well conformity with the existing work. It is seen that even the tall Cu vias are not going to significantly affect the performance of MWCNT bundle interconnects. Twice the minimum width global level interconnects are the optimal choice to achieve the maximum delay advantage using MWCNT bundle interconnects in comparison with Cu-based interconnects. Finally, our analysis shows that from the performance and signal integrity perspective, the large diameter MWCNT bundles are a suitable alternative to both small diameter MWCNT bundles and copper interconnects for future integrated circuit technology generations.

Minimizing Thermal Disparities during Placement in 3D ICs

During the Computer Aided Physical Design Cycle and specifically for high-performance VLSI circuits, on-chip power density plays a major role. The catalyst factors are increased scaling of technology, increasing number of components, higher frequency and bandwidth. The consumed power is usually converted into dissipated heat, affecting the performance and reliability of a chip. Moreover, recent trends in VLSI design entails the stacking of multiple active layers into a monolithic chip. These 3D chips have significantly larger power densities than their 2D counterparts. In this paper, we consider the placement of standard cells and gate arrays (modules) under thermal considerations. Our contribution includes a novel algorithm for placement of the gates or cells in the different active layers of a 3D IC such that: (i) the temperatures of the modules in each of the active layers is uniformly distributed, (ii) the maximum temperatures of each of the active layers is not too high, (iii) the maximum temperatures of the layers vary in a non-increasing manner from bottom layer to top layer to ensure an efficient heat dissipation of the whole chip. Experimental results on randomly generated and standard MCNC and ISPD benchmark instances are quite encouraging.

Thermal-Aware Placement of Standard Cells and Gate Arrays: Studies and Observations

In high-performance VLSI circuits, the on-chip power densities are playing dominant role due to increased scaling of technology, increasing number of components, frequency and bandwidth. The consumed power is usually converted into dissipated heat, affecting the performance and reliability of a chip. In this paper, we consider the placement of standard cells and gate arrays (modules) under thermal considerations. Our contributions include: (i) an algorithm for optimal placement of the gates or cells to minimize the possible occurrence of hot spots, (ii) results of sensitivity analysis of thermal characteristic of a layout with respect to the power densities of the modules in the layout, and identifying three classes of modules, and (iii) an algorithm for optimal placement of modules, with minimum possible occurrence of hot spots, and reasonable estimated interconnect lengths. Experimental results on randomly generated and standard benchmark instances are quite encouraging.

A Low Latency Scalable 3D NoC Using BFT Topology with Table Based Uniform Routing

Due to the limitations of traditional bus based systems, Network-on-Chip (NoC) has evolved as the most dominanttechnology in the paradigm of communication-centric revolution, where, besides the computation, inter-communication between the cores is an indispensable aspect of a SoC. Furthermore, the emergence of three dimensional integrated circuits (3D-ICs) has resulted in better performance, functionality, and packaging density compared to traditional planar ICs. The amalgamation of these two technologies, the 3D NoC architecture, can combine the benefits of these two new domains to offer an unprecedentedperformance gain. In this paper, we present a new 3D topological NoC design based on the butterfly fat tree (BFT) topology with an efficient table based uniform routing algorithm for 3D NoC. Extensive simulation experiments have been performed for BFT and compared to mesh, torus, butterfly and flattened butterfly topologies against four performance metrics viz. overall average latency, overall average acceptance rate, overall minimum acceptance rate, and average hop counts. There are significant latency improvements of 43-89 %, 83-88 %, 46-96 %, and 31-95 % over other topologies respectively. Average hop count is improved by 30 % and 13 % over mesh and torus. Also, there are improvements in average acceptance rate and minimum acceptance rate of 1-8 % and 5-14 % respectively for flattened butterfly and 6-9 % and 6-13 % over torus. Results evidently show that BFT is a very good choice for low network latency and faster communication.

An ABCD parameter-based modeling and analysis of crosstalk induced effects in single-walled carbon nanotube bundle interconnects

Single-walled carbon nanotubes (SWCNTs) have the potential to revolutionize the interconnects in future nanoscale integrated circuits. In the proposed work, crosstalk effects are investigated in SWCNTs at 21 nm and 15 nm technology nodes for intermediate as well as global interconnects. An ABCD parameter based approach has been used to investigate crosstalk delay and noise in both sparse as well as dense SWCNT bundled interconnect system. It is evident from the simulation results that the proposed model is not only 100% accurate but also almost 10 times faster than SPICE. The worst case crosstalk induced delay and peak crosstalk noise voltages for SWCNT bundle interconnects are compared to those of conventional copper (Cu) interconnects at the intermediate as well as global level interconnects. Simulation results also confirm that dense SWCNTs are always ahead of sparse SWCNTs with respect to performance advantage numbers over copper for every levels of interconnects and irrespective of technology nodes. As far as the worst case peak crosstalk noise is concerned, there is a critical length after which the performance of the dense SWCNT bundles is better than that of its sparse counterpart. Proposed model, analysis, along with supportive simulation results prove that dense SWCNT bundled interconnect is one of the most promising alterative interconnect solution for future generation of nanoscale circuits compared to copper with respect to performance as well as signal integrity issues.

A Novel Routing Algorithm for On-Chip Communication in NoC on Diametrical 2D Mesh Interconnection Architecture

To meet the design productivity, scalability and signal integrity challenges of next-generation system designs, a structured and scalable interconnection architecture, network on chip (NoC), has been proposed recently to solve the complex on-chip communication problem. In an NoC, the communication among different nodes is achieved by routing packets through a pre-designed network fabric according to some architecture rather than wires. In Diametrical 2D Mesh architecture, advantages of routing include smaller network diameter as well as larger bisection width. Again, fast network access requires a well-constructed optimal routing algorithm. Our proposed routing algorithm ensures that the packet will always reach the destination through the shortest path and it is deadlock free.

Reversible circuit synthesis using ACO and SA based Quine-McCluskey method

With the tremendous growth in VLSI technology in recent years, the Integration density of the transistors has reached billions causing the scaling of transistors to touch the subatomic dimension in deep submicron regime where laws of classical physics can not survive. Due to inherent information loss and other factors associated with irreversible computing, reversible circuits are becoming more and more important in terms of computing for present and future days. However, due to several factors, known synthesis approaches of classical Boolean logic like Karnaugh Map and Quine-McCluskey method cannot be applied directly to synthesize a reversible logic. In this paper, we propose a stochastic procedure to synthesize a reversible circuit. This procedure is based on a modified version of classical Quine-McCluskey method and is being used under the wrapper of two intelligent stochastic search techniques, Simulated Annealing and Ant Colony Optimization. The experimental results are quite encouraging.

Revisiting fidelity: a case of elmore-based Y-routing trees

The dominance of interconnect delay in VLSI circuit design is well-known. Construction of routing trees in recent times has to take care of the timing issues for faster design convergence. Thus there is immense scope of research in design and performance of interconnects. Our current work encompasses two aspects of this research. On one hand, we consider the construction of cost-effective global routing trees with the recently introduced Y-interconnects, and on the other hand, we utilize this framework for verifying the supremacy of the Elmore delay estimate for its high fidelity. In order to ensure accurate computation of fidelity, (i) we propose new statistically proven formulae for fidelity, and (ii) compute the fidelity values based on delay estimates for optimal and near-optimal trees. Our experiments on several randomly generated problem instances and benchmarks confirm once again the supremacy of fidelity of Elmore delay over that of linear delay.

A Highly Parameterizable Simulator for Performance Analysis of NoC Architectures

Network, wireless, and multimedia applications executing on embedded chips demand massive data processing with lesser power consumption today. Journey of a new paradigm in the domain of parallel processing - Network-on-Chip (NoC) starts here. But unlike its simpler look both the design and test costs for this kind of real many-core chips are too high. So efficient and accurate performance estimation tools with respect to the real application ASICs are needed for system level optimization and performance analysis in a cost-effective and flexible way. Simulator that allow exploring the best design options for a system before actually building it has been becoming inevitable in system design and optimization flows. Very few simulators have been developed so far addressing such problems. Some of them are popular with its better accuracy and others with a large set of configurable architectural parameters and traffic options. In this paper, a novel GUI based highly parameterizable NoC simulator has been proposed designed using Qt and System C that is capable of handling real embedded workload traces with custom task allocation support for early exploration of application specific Network-on-Chips.