Sabyasachi Deyati

RAVAGE: Post-silicon validation of mixed signal systems using genetic stimulus evolution and model tuning

With trends in mixed-signal systems-on-chip indicating increasingly extreme scaling of device dimensions and higher levels of integration, the tasks of both design and device validation is becoming increasingly complex. Post-silicon validation of mixed-signal/RF systems provides assurances of functionality of complex systems that cannot be asserted by even some of the most advanced simulators. We introduce RAVAGE (from “random;” “validation;” and “generation”), an algorithm for generating stimuli for post-silicon validation of mixed-signal systems. The approach of RAVAGE is new in that no assumption is made about any design anomaly present in the DDT; but rather, the stimulus is generated using the DUT itself with the objective of maximizing the effects of any behavioral differences between the DUT (hardware) and its behavioral model (software) as can be seen in the differences of their response to the same stimulus. Stochastic test generation is used since the exact nature of any behavioral anomaly in the DUT cannot be known a priori. Once a difference is observed, the model parameters are tuned using nonlinear optimization algorithms to remove the difference between its and the DUTs responses and the process (test generation→tuning) is repeated. If a residual error remains at the end of this process that is larger than a predetermined threshold, then it is concluded that the DUT contains unknown and possibly malicious behaviors that need further investigation. Experimental results on an RF system (hardware) are presented to prove feasibility of the proposed technique.

A reusable BIST with software assisted repair technology for improved memory and IO debug, validation and test time

As silicon integration complexity increases with 3D stacking and Through-Silicon-Via (TSV), so does the occurrence of memory and IO defects and associated test and validation time. This ultimately leads to an overall cost increase. On a 14nm Intel SOC, a reusable BIST engine called Converged-Pattern-Generator-Checker (CPGC) are architected to detect memory and IO defects, and combined with the software assisted repair technology to automatically repair memory cell defects on 3D stacked Wide-IO DRAM. Additionally, we also present the CPGC gate count, power, simulation, and silicon results. The reusable CPGC IP is designed to connect to a standard IP interface, which enables a quick turn-key SOC development cycle. Silicon results show CPGC can speed up validation by 5x, improve test time from minutes down to seconds, and decrease debug time by 5x including root-cause of boot failures of the memory interface. CPGC is also used in memory training and initialization, which makes it a critical part of Intel SOC.

Targeting hardware trojans in mixed-signal circuits for security

The proliferation of third-party silicon manufacturing has increased the vulnerability of integrated circuits to malicious insertion of hardware for the purpose of leaking secret information or even rendering the circuits useless while deployed in the field. A key goal is to detect the presence of such circuits before they are activated for subversive reasons. One way to achieve this is to detect the presence of parasitic loads on internal nodes of a victim circuit. However, such detection becomes difficult in the presence of normal process variations of the silicon manufacturing process itself. In this work, we show how high-resolution detection of parasitic loads on internal circuit nodes can be achieved using a combination of test stimulus design and design-for-Trojan detection techniques. We illustrate our ideas on digital as well as analog/mixed-signal circuits and point to directions for future research.

High Resolution Pulse Propagation Driven Trojan Detection in Digital Logic: Optimization Algorithms and Infrastructure

Insertion of malicious Trojans into outsourced chip manufacturing generally results in increased capacitances of internal circuit nodes that have been tapped for node controllability and observability by malicious circuitry. Current path delay measurement and side channel Trojan detection techniques are unable to detect Trojans that present low loading to such tapped circuit nodes, especially in the presence of large manufacturing process variations. In this paper, a high-resolution Trojan detection method for digital logic based on pulse propagation is developed. The method exhibits 25X -- 30X higher diagnostic resolution (ability to measure small capacitive loads on internal circuit nodes) as compared to current path delay based Trojan detection techniques in the presence of significant manufacturing process variations. Further, a key benefit is that theoretically, as opposed to path delay measurement based methods, the diagnostic resolution of the test approach is independent of circuit logic depth over and above the benefits already mentioned above. Test methods and test infrastructure compatible with existing scan based techniques are described. Simulation results are presented to prove the viability and effectiveness of the proposed Trojan detection scheme and especially for circuits with large logic depths (35-70 gates) suffering from worst case process variation effects.

VAST: Post-Silicon VAlidation and Diagnosis of RF/Mixed-Signal Circuits Using Signature Tests

Post-silicon validation of RF/mixed-signal circuits is challenging due to the need to excite all possible operational modes of the DUT in order to establish equivalence between its specified and observed behaviors and to ensure that the DUT does not produce any unexpected behaviors that can lead to system failure. In this research, we first develop a methodology for determining if the DUT contains behaviors that are not explicitly included in its behavioral model. A complex (optimized) test waveform is applied to the DUT and its test response signature is captured. It is seen that in the presence of unexpected DUT behaviors, the residual error in the test response signature from that defined by the model, cannot be minimized below a certain threshold by manipulating the model parameters in any way. If however, it is determined that the model is adequate but the signature is different from the expected, then a procedure is developed for determining which sub module is responsible for the difference (i.e. causes the system level specifications to be different from that specified by the behavioral model). Experiments on an RF transceiver are performed to demonstrate the effectiveness of the proposed validation and diagnosis approach.

Atomic model learning: A machine learning paradigm for post silicon debug of RF/analog circuits

As RF design scales to the 28nm technology node and beyond, pre-silicon simulation and verification of complex mixed-signal/RF SoCs is becoming intractable due to the difficulties associated with simulating diverse electrical effects and design bugs. As a consequence, there is increasing pressure to develop comprehensive post-silicon test and debug tools that can be used to identify design bugs and improve modeling of complex electrical nonidealities observed in silicon. Often, it is not known a-priori what these bugs are and how they can be modeled, significantly complicating the debug process. In this research, a new atomic model learning approach is proposed that uses supervised learning techniques to diagnose design bugs and learn unknown module-level behaviors. Nonideality modeling artifacts called model atoms are inserted into different nodes of the design signal flow paths to learn unknown behaviors along those paths. Under the assumption that the design bug is localized, it is shown that the source of the bug can be identified with high resolution even when the nature of the bug is unknown. The method has been applied to a conventional wireless as well as a polar radio transmitter and key results that demonstrate usefulness and feasibility of the proposed approach are presented.

Validation signature testing: a methodology for post-silicon validation of analog/mixed-signal circuits

Due to the use of scaled technologies, high levels of integration and high speeds of todays mixed-signal SoCs, the problem of validating correct operation of the SoC under electrical bugs and that of debugging yield loss due to unmodeled multi-dimensional variability effects is extremely challenging. Precise simulation of all electrical aspects of the design including the interfaces between digital and analog circuitry, coupling across power and ground planes, crosstalk, etc., across all process corners is very hard to achieve in a practical sense. The problem is expected to get worse as analog/mixed-signal/RF devices scale beyond the 45nm node and are more tightly integrated with digital systems than at present. In this context, a post-silicon validation methodology for analog/mixed-signal/RF SoCs is proposed that relies on the use of special stimulus designed to expose differences between observed DUT behavior and its predictive model. The corresponding error signature is then used to identify the likely “type” of electrical bug and its location in the design using nonlinear optimization algorithms. Results of trial experiments on RF devices are presented.

Adaptive testing of analog/RF circuits using hardware extracted FSM models

The test generation problem for analog/RF circuits has been largely intractable due to the fact that repetitive circuit simulation for test stimulus optimization is extremely time-consuming. As a consequence, it is difficult, if not impossible, to generate tests for practical mixed-signal/RF circuits that include the effects of tester inaccuracies and measurement noise. To offset this problem and allow test generation to scale to different applications, we propose a new approach in which FSM models of mixed-signal/RF circuits are abstracted from hardware measurements on fabricated devices. These models allow accurate simulation of device behavior under arbitrary stimulus and thereby test stimulus generation, even after the device has been shipped to a customer. As a consequence, it becomes possible to detect process shifts with fine granularity and regenerate tests to adapt to process perturbations in a dynamic manner without losing test accuracy. A complete methodology for such adaptive testing of mixed-signal/RF circuits is developed in this paper. Simulation results and hardware measurements are used to demonstrate the efficacy of the proposed techniques.

Challenge Engineering and Design of Analog Push Pull Amplifier Based Physically Unclonable Function for Hardware Security

In the recent past, Physically Unclonable Functions (PUFs) have been proposed as a way of implementing security in modern ICs. PUFs are hardware designs that exploit the randomness in silicon manufacturing processes to create IC-specific signatures for silicon authentication. While prior PUF designs have been largely digital, in this work we propose a novel PUF design based on transfer function variability of an analog push-pull amplifier under process variations. A differential amplifier architecture is proposed with digital interfaces to allow the PUF to be used in digital as well as mixed-signal SoCs. A key innovation is digital stimulus engineering for the analog amplifier that allows 2X improvements in the uniqueness of IC signatures generated over arbiter-based digital PUF architectures, while maintaining high signature reliability over +/- 10 % voltage and -20 to 120 degree Celsius temperature variation. The proposed PUF is also resistive to model building attacks as the internal analog operation of the PUF is difficult to reverse-engineer due to the continuum of internal states involved. We show the benefits of the proposed PUF through comparison with a traditional arbiter-based digital PUF using simulation experiments.

Trojan detection in digital systems using current sensing of pulse propagation in logic gates

Outsourcing of chip manufacturing to untrusted foundries and using third party IPs in design, have opened the possibility of inserting malicious hardware Trojans into the circuit. As excitation of Trojan is extremely rare, it is almost impossible to detect Trojans with functional logic testing. We need to detect Trojans without actually activating it (side channel analysis). Hardware Trojan circuit get inputs from low transition probability nodes of the original circuit. Tapping of these nodes for creating Trojan inputs increase capacitive load at those nodes. We have developed a very high resolution pulse propagation technique to capture this extra capacitance at Trojan affected nodes. This technique provides 20-25X higher diagnostic resolution than path delay analysis in the presence of significant manufacturing process variation. Pulse propagation based Trojan detection is independent of logic depth in the path. As the logic depth increases other state of the art Trojan detection schemes loses accuracy. Though the scheme appears simple, it is not so straight forward to generate and apply the pulse inputs on chip at the desired locations and capture them at designated locations with high accuracy in presence of high fan out nodes in the design. We have developed a very high resolution current sensing scheme to detect pulse propagation through logic gates. A single sensor can sense pulse at multiple locations. The entire scheme of pulse based Trojan detection has been integrated into JTAG boundary scan scheme with minimal area overhead to provide a complete solution for Hardware Trojans.