Sadanand V. Deshpande

Trimming of hard-masks by gaseous Chemical Oxide Removal (COR) for sub-10 nm gates/fins, for gate length control and for embedded logic

A method for formation and control of silicon gates or fins uses trim of a hard mask by a new gaseous oxide etch. The method decouples final feature size from lithography and from the RIE resist trim/oxide mask open processes. Logic blocks with two separately controlled gate lengths and dielectric thicknesses are embedded on chip. COR control has achieved final size sprads of 1 to 2 nm using measurements from either the factory CDSEM or from a scatterometer integrated on the process tool.

Performance analysis and modeling of deep trench decoupling capacitor for 32 nm high-performance SOI processors and beyond

In this paper, we present a systematic performance study and modeling of on-chip deep trench (DT) decoupling capacitors for high-performance SOI microprocessors. Based on system-level simulations, it is shown that the DT decoupling capacitors (decap) offer significant area advantage over the other two conventional decoupling capacitors - Metal-oxide-semiconductor (MOS) and Metal-Insulator-Metal (MIM). The fabrication process flow of DT decap is borrowed from regular eDRAM process and adds no additional process cost to processors that utilize large eDRAM cache [1]. We demonstrate that, with new process innovations such as introduction of High-k/metal gate and new plate doping methodology, there is significant reduction in equivalent series resistance (ESR) of the trench resulting in ~3.5X improvement in half capacitance frequency for 32nm node. Further, with 22nm technology, improved ESR, DT Decaps performance is significantly enhanced, hence showing that DT-decaps can be reliably used for technology beyond 32nm.

Implementation of Robust Nickel Alloy Salicide Process for High-Performance 65nm SOI CMOS Manufacturing

Addition of Pt to Ni silicide produces a robust [NixPt(1-x)]Si, which shows an improved morphological stability, an important reduction in encroachment defect density, a reduced tendency to form NiSi2 and significant variations in monosilicide texture without degrading the device performance or the yield of high-performance 65 nm SOI technologies.

Advanced junction formation for sub-32nm logic devices

This paper is meant to be a general overview of recent advances in new processes and process tooling (implant and anneal) for advanced junction formation. Also included are details of impact of novel implant processes, such as cold implant and pre-amorphization (PAI) implants on Nickel Silicide (NiSi) formation. We will also discuss subtle impacts of wafer temperature during ion implantation on channel stress retention and shallow junctions in todays advanced device nodes.

Characterization of linewidth variation on 248- and 193-nm exposure tools

The line-width variation of a 193 nm lithographic process utilizing a 0.60 NA scanner and a binary reticle is compared to that of a 248 nm lithographic processes utilizing a 0.68 NA scanner and a variety of reticle technologies. These include binary, attenuated PSM with assist features and alternating PSM reticles. Despite the fact that the 193 nm tool has a lower NA and that the data was generated using a binary reticle, the 193 nm lithographic process allows for the line-width values to be pushed lower than previously achieved with 248 nm lithographic processes. The 3-sigma values from 4000 electrical line-width measurements per wafer (160 measurements per 25*25 mm field, 25 fields per wafer) were calculated for different mask features. The 193 nm process was capable of reaching line-widths needed for future generations of advance logic chips. Compared to the 193 nm process utilizing a binary reticle, only the 248 nm processes utilizing either an attenuated PSM with assist features or an alternating PSM reticle had similarly low line-width variation. The 248 nm processes utilizing a binary reticle had higher line-width variation even at larger poly gate conductor line-widths.