Wesley C. Natzle

High-performance symmetric-gate and CMOS-compatible V/sub t/ asymmetric-gate FinFET devices

Double-gate FinFET devices with asymmetric and symmetric polysilicon gates have been fabricated. Symmetric gate devices show drain currents competitive with fully optimized bulk silicon technologies. Asymmetric-gate devices show |V/sub t/|/spl sim/0.1 V, with off-currents less than 100 nA/um at V/sub gs/=0.

Extreme scaling with ultra-thin Si channel MOSFETs

We examine the scaling limits for planar single gate technology using the ultra-thin Si channel MOSFET. Characteristics for extreme scaled devices with physical gate lengths down to 6 nm and SOI channels as thin as 4 nm are presented. For the first time, we report ring oscillators with 26 nm gate lengths and ultra-thin Si channels.

Feedforward of mask open measurements on an integrated scatterometer to improve gate linewidth control

As feature geometries decrease, the budgeted error for process variations decreases as well. Keeping these variations within budget is especially important in the area of gate linewidth control. Because of this, wafer-to-wafer control of gate linewidth becomes increasingly necessary. This paper shows results from 300 mm wafers with 90 nm technology that were trimmed during the gate formation process on an etch platform. After the process that opened the gate hard mask and stripped the resist, the wafers were measured using both an integrated scatterometer and a stand-alone CD-SEM. The measurements were then used to determine the appropriate amount to be trimmed by the Chemical Oxide Removal (COR) chamber that is also integrated onto the etch system. After the wafers were trimmed and etched, they were again measured on the integrated scatterometer and stand-alone CD-SEM. With the CD-SEM as the Reference Measurement System (RMS), Total Measurement Uncertainty (TMU) analysis was used to optimize the Optical Digital Profilometry (ODP) model, thus facilitating a significant reduction in gate linewidth variation. Because the measurement uncertainty of the scatterometer was reduced to a level approaching or below that of the RMS, an improvement to TMU analysis was developed. This improvement quantifies methods for determining the measurement uncertainty of the RMS under a variety of situations.

Trimming of hard-masks by gaseous Chemical Oxide Removal (COR) for sub-10 nm gates/fins, for gate length control and for embedded logic

A method for formation and control of silicon gates or fins uses trim of a hard mask by a new gaseous oxide etch. The method decouples final feature size from lithography and from the RIE resist trim/oxide mask open processes. Logic blocks with two separately controlled gate lengths and dielectric thicknesses are embedded on chip. COR control has achieved final size sprads of 1 to 2 nm using measurements from either the factory CDSEM or from a scatterometer integrated on the process tool.

Systematic study of work function engineering and scavenging effect using NiSi alloy FUSI metal gates with advanced gate stacks

We present a systematic examination of work function modulation and scavenging effect on fully silicided gates using different NiSi alloys (Ti, Hf, Zr, Pd, Pt, and Al) as well as different phases (Ni31Si12 and Nirich-Pt-Si). It is shown that the interface layer between gate FUSI and dielectric is the key to modulate the work function. FUSI alloys were able to prevent Fermi level pining on HfSiO and HfO2 by modification of the top interface. A ~400 meV work function shift was achieved toward the conduction band edge using NiAlSi demonstrating a mobility of 300 cm2/Vs at peak, matching NiSi control devices on Hfx SiOy. Interface engineering with FUSI alloy gate has not only shown threshold voltage modulation but also enabled further gate oxide scaling (0.15 ~ 0.2nm) compared to NiSi control device. Additional gate oxide scaling is due to the increase of effective dielectric constant in the FUSI gate stack. TEM, EELS, and EDX showed that work function modulation is attributed to the Al pile up at interface. Ni rich silicide FUSI gates showed a ~250mV shift from mid gap toward valence band edge with elimination of Fermi-level pining by modification of the top dielectric interface

70 nm Damascene-Gate MOSFETs with Minimal Polysilicon Gate-Depletion

In this work, for the first time, we present very high performance CMOS devices with 70 nm gate length and 2.2 nm Tinv effective gate oxide thickness fabricated using a damascene-gate process. Poly-Si gate electrodes are used with minimal poly depletion due to the de-coupling of the gate implantation from the source and drain implantation in the damascene-gate process. Saturation transconductance of 722 μS/μm for nMOSFETs and 354 μS/μm for pMOSFETS are achieved. ION for a 1.5 V supply is 0.9 mA/um for the nMOSFETs and 0.43 mA/um for the pMOSFETs with IOFF of both devices is 20 nA/um. The reduced junction capacitance and minimal poly-Si gate depletion in the damascene process resulted in a measured delay per stage of 8.6 ps for a 101-stage CMOS inverter ring oscillator at 1.5 V supply.