Gaurav Kaushal

Vertical Silicon Nanowire Gate-All-Around Field Effect Transistor Based Nanoscale CMOS

In this letter, we investigate a novel vertical silicon nanowire-based (NW) complementary metal-oxide-semiconductor (CMOS) technology for logic applications. The performance and the behavior of two- and single-wire CMOS inverters are simulated and analyzed. We show that vertical NW based CMOS offers a reduction of up to 50% in layout area, along with delay reductions of 50% (two wire) and 30% (single wire) compared with fin-shaped field effect transistor (FinFET) technology. The results show that vertical NW CMOS technology has a very high potential for ultralow-power applications with a power saving of up to 75% and offers an excellent overall performance for deca-nanoscale CMOS.

Vertical Nanowire CMOS Parasitic Modeling and its Performance Analysis

In this paper, the analytical models of parasitic resistance and capacitance of vertical nanowire (VNW) FET are presented, considering device structural asymmetry. These models are then used to analyze the effect of channel, source-drain extension lengths, and nanowire diameter on device and VNW CMOS performance for 15 nm node. We find that the asymmetry in structure (between top and bottom electrodes) leads to asymmetric parasitic resistances and capacitances that play an important role in determining the circuit delays. Thus our models help to quantify the role of parasitics on VNW device and CMOS performance having device asymmetry. Further, these parasitic models have high potential for use in developing a compact model of a complete device for VNW circuit simulations.

Device Circuit Co-Design Issues in Vertical Nanowire CMOS Platform

In this letter, we investigate the effect of device and layout parasitics on circuit performance of vertical nanowire (VNW) CMOS technology. We evaluate the effect of source-drain extension (S/Dext) scaling and device asymmetry on device and circuit performances for 15 nm VNW CMOS. It is seen that, due to reduced series resistance, circuit delay continues to improve with S/Dext down to 10 nm, despite increased parasitic capacitances. Also, we show that asymmetry between top and bottom electrodes plays a strong role in determining circuit delay, while layout-dependent parasitics are of secondary importance. The results show that delay is increased by 65% with top electrode as source, which is attributed to increase in series resistance and gate-drain overlap capacitances. The comparison of VNW and FinFET CMOS shows nearly 40% delay reduction, highlighting excellent potential of VNW CMOS for 15 nm and below technology nodes.

A Degradation Model of Double Gate and Gate-All-Around MOSFETs With Interface Trapped Charges Including Effects of Channel Mobile Charge Carriers

The reliability of multigate metal-oxide-semiconductor (MOS) devices is an important issue for novel nanoscale complementary MOS (CMOS) technologies. We present an analytic degradation model of double-gate (DG) and gate-all-around (GAA) MOS field-effect transistors (MOSFETs) in the presence of localized interface charge. Furthermore, we consider the effect of channel mobile charge carriers that significantly enhances the accuracy of our model. In our model, an accurate definition of threshold voltage in terms of minimum channel carrier density is used. The proposed model accurately depicts the effect of hot-carrier-induced degradation (HCD) on the surface potential, threshold voltage, and subthreshold swing. The results show a good agreement with the technology computer-aided design (TCAD) SENTAURUS device simulator over a wide range of device parameters. The modeling results show that the HCD effect become more dominant for scaled-down DG/GAA MOSFET devices. A comparative HCD degradation analysis carried for DG and GAA MOSFETs to understand their reliability limits show that GAA has greater immunity to HCD than DG MOSFET. This highlights model accuracy and provides crucial insights for HCD-tolerant multigate MOSFET design.

Novel Design Methodology Using

In this paper, the impact of nanowire source/drain extension, diameter, and channel length on nanowire (NW) device performance is investigated. We present a novel approach using the extension length as tuning parameter to match the drive current of n- and p-FET in NW CMOS logic applicable down to 10-nm gate length. Our approach overcomes the drive matching issue in NW/FinFET based CMOS circuits. We show that, in comparison to conventional CMOS, where the number of NWs/fins in p-FET is used to match n-FET drive, the proposed approach provides a significant reduction in circuit active area and power dissipation. When compared to conventional CMOS inverter, the proposed approach shows 20% lower area, and 35% saving in power in case of NW CMOS inverter. Our results show that extension length tuned-CMOS has an excellent option for low-power applications in both NW and FinFET technologies.

L_{\bf EXT}

In this brief, we have analyzed the response of silicon-nanowire (Si-NW) gate-all-around (GAA) field-effect transistor to total ionizing dose (TID) effects and assessed the impact of single-event effects (SEEs) in simple inverter circuit built from such devices. The analysis of radiation effects is carried out with 3-D technology computer-aided design simulations. Reliability of n-channel and p-channel Si-NW MOSFET is investigated for TID effects with gamma ray exposure. The transient effects at the device level are studied for alpha particle and heavy-ion strikes. It is found that Si-NW MOSFET is inherently hardened to TID effects. This result is in concordance with the earlier reported experimental results. However, we found that Si-NW CMOS inverter is not as tolerant to SEE, as Si-NW MOSFET is to TID. This study highlights the need for radiation-hardened Si-NW FET circuits against SEE.

Sizing in Nanowire CMOS Logic

In this work, the parasitic resistance components of Vertical nanowire FET (VNW) are analytically modeled considering the gate and device asymmetry. Further the models are used to analyze the scaling performance with varying channel length and source-drain extension length. The top and bottom electrode asymmetry leads to asymmetric parasitic resistances which determine gate overdrive or device current and the circuit delay. Thus the models can be used to optimize and quantify the VNW device performance.

Radiation Effects in Si-NW GAA FET and CMOS Inverter: A TCAD Simulation Study

In this work we investigate novel vertical Silicon nanowire (NW) based CMOS technology for logic applications. The performance and behaviour of two nanowire and single nanowire vertical CMOS inverter are simulated and analysed. It is seen that vertical NW MOSFET has a significant performance gain over corresponding FinFET technology. We show that nanowire based vertical CMOS offer up to 80% reduction in layout area, and nearly one order of magnitude reduction in power at the cost of 15% (two wire) and 40% (single diameter single wire) increased delay. The results show that vertical nanowire based CMOS technology has very high potential for ultra-low power applications and offers excellent overall performance for deca-nanoscale CMOS.