Salem Abdennadher

Challenges in High Speed Interface Testing

There is a common trend towards the incorporation of Serial Interfaces into Systems-on-Chips (SoC), both for inter-chip and intra-chip high-bandwidth data transfers. Serial interfaces have the same channel medium drives as Parallel interfaces and provide increased data rates and fewer interconnects. High speed serial interfaces, such as SATA, Hyper- Transport, and PCI Express, are becoming pervasive in networking and in computer equipment. Some computer interfaces are converging to communications interfaces. Today, speeds for these serial interfaces range from 1.5 to 3.3 Gbps; in the near future, they will reach 6.4 Gbps and beyond (Figure 1).

Improving IO test and system evaluation via data sharing

High speed I/O circuits are becoming increasingly critical as technology scales to increase system bandwidth and decrease power dissipation, die area and system cost. Highly integrated SOCs are currently equipped with large numbers of serial links to enable processing of high bandwidth data streams. There are two major challenges to continued scaling of highspeed I/Os: band-limited channels and timing uncertainty that require a good knowledge on customer system usage. In addition the increase push for customer differentiation and OEMs pushing more designs to low cost and less skilled design teams adds to the challenge. Adequate learning data sharing between customers and silicon provider is key in these emerging markets to meet quality and Time to Market targets.

Effects of Advances in Analog, Mixed Signal and IO Circuits on Test Strategies

This paper focuses on high level integration of analog on todays products. We will present the paradigm change required to test these circuit from ATE driven solutions to DFT/BIST/BOST techniques. We will present industrial examples of implementation and silicon results. The examples will range from PLL Testing using ATE approaches and on-chip jitter measurements (TDC based approach) to ADC testing using on chip ramp generation and off chip active TIU (Test Interface Unit) approach to PCIe testing using capable tester to DFT based methods. The talk will focus on what techniques performed well and provided a good alternative solution and which ones resulted in more yield loss or high DPM escapes.

Practices in High-Speed IO testing

With advances in VLSI technology, process, packaging, and architecture, SoC dies continue to increase in complexity. These advances have resulted in an unprecedented rise in design marginalities, manufacturing flaws and customer returns in SoCs with High-Speed IO circuits. This situation presents a challenge to develop sophisticated but low-cost test solutions. DFT-based test methods offer solutions to this challenge. This tutorial paper provides a summary of industry practices in DFT-based approaches to testing High-Speed IOs and their comparison with the specification-based tests.

Practices in Testing of Mixed-Signal and RF SoCs

The presentation includes an overview of challenges in testing analog, mixed signal, and RF SoCs, and presents alternative solutions to ATE functional testing for products that are suitable for high volume manufacturing. This talk presents a different level of granularity within mixed signal SoC testing by abstracting the systems in terms of product types, specifications, interfaces, or building blocks. This way, the final testing of the SoC becomes an aggregation of the test techniques targeted for particular product types, interfaces, and building blocks incorporated in the system. Several industrial examples of production testing of mixed-signal and RF devices are presented in this talk