Samar K. Saha

Subthreshold Analog/RF Performance Enhancement of Underlap DG FETs With High- K Spacer for Low Power Applications

This paper presents a systematic study of the subthreshold analog/RF performance for underlap double gate (UDG) NMOSFETs using high dielectric constant (k) spacers. The conventional UDG-NMOSFETs offer reduced short-channel effects along with improved subthreshold analog/RF performance at a cost of higher distributed channel resistance and low on current. In this paper, we show that these drawbacks can be alleviated effectively by using high-k spacers without any severe degradation in the subthreshold analog/RF performance. In order to show the improvement in the device performance, we have studied the effect of high-k spacers on different subthreshold analog figures of merit such as the transconductance, transconductance generation factor, output resistance, and the intrinsic gain for different values of k . Moreover, we have analyzed the RF performance as a function of intrinsic capacitance and resistance, transport delay, inductance, cutoff frequency, and the maximum oscillation frequency. In order to assess the gain bandwidth (GBW) product, the circuit implementation of the UDG-NMOSFETs with different high-k spacers was performed on a common source amplifier. Our results show an improvement in the GBW of about 38% for the devices with high- k spacers compared to its low- k counterpart.

Design Considerations for Sub-90-nm Split-Gate Flash-Memory Cells

This paper presents a systematic methodology to design efficient sub-90-nm split-gate Flash-memory cells and optimize the cell performance within the presently known scaling constraints. The device-simulation results show that the high-performance sub-90-nm split-gate cells can be realized by a proper optimization of the channel and asymmetric halo-doping profiles and shallow source/drain junctions. In this paper, the halo-and channel-doping profiles were optimized to achieve the target drain-programming voltage Vsp = 6.5 V for an efficient cell programming, whereas keeping the breakdown voltage BV > Vsp with tolerable leakage currents. It is shown that, using the properly optimized technology parameters, 65-nm split-gate Flash memory can be achieved with cell-read current, Ir1 ap 235 mum, programmed cell-leakage current, Ir0 < 2.2 nA/ mum at the read condition, time-to-program ap 30 mus, and time-to-erase ap 40 mus. This paper clearly demonstrates the feasibility of high-performance 65-nm split-gate Flash-memory cells.

Analysis of High-

In this paper, asymmetric underlap double-gate (AUDG) MOSFET is studied to analyze the influence of high-k spacer on the intrinsic device parameters. The AUDG-MOSFET architecture offers better device performance, particularly, drain-induced barrier lowering in contrast to the conventional double-gate (DG)-MOSFET. However, the ON current and the distributed resistances for the device increase considerably. The analysis of the device presented here shows that the detrimental effects of the device can be effectively eliminated using high-k spacers. To evaluate the device performance and to study the improvement associated with the use of high-k spacers, different intrinsic parameters are analyzed. These parameters include transconductance (g_m), transconductance generation factor (g_m/I_d), intrinsic gain (g_mr_o), intrinsic capacitance (C_gd, C_gs), resistance (R_gd, R_gs), transport delay (τ_m), inductance (L_sd), cutoff frequency (f_T), and the maximum frequency of oscillation (f_max), gain bandwidth product, and inverter delay.

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The increasing usage of flash memory in mobile applications is pushing the scaling limit of Flash memory technology. This paper presents a systematic scaling methodology, architecture, optimization strategy, and performance of sub-90 nm split-gate flash memory cells. The device simulation results show that the split-gate cells can be scaled to 90 nm node and below using shallow source/drain junctions and a highly localized source-halo in conjunction with channel engineering. Using properly optimized technology parameters, sub-90 nm cells with tolerable leakage current and efficient time-to-program and time-to-erase can be achieved

Spacer Asymmetric Underlap DG-MOSFET for SOC Application

In this paper, the harmonic distortion (HD) in the underlap double-gate MOSFETs (UDG-MOSFETs) with high- k spacers is analyzed. The HD occurs due to the nonlinearity in the device performance and therefore, a detailed analysis of the HD as a function of spacer dielectric constant (k) is critical to ensure device reliability for RF performance. In this paper, the analysis is performed for the primary components, the second-order distortion (HD2), and the third-order distortion (HD3) along with the total HD. The parameters analyzed for the HD study of the UDG-MOSFETs with high- k spacers are the drain current, the transconductance, and the transconductance generation factor. The results of the analysis suggest a reduction in the distortion phenomenon for the high- k spacer devices, thereby ensuring reliability of these devices for RF applications. Also, a detailed analysis of HD2 and HD3 as a function of k of the high- k spacers are performed using UDG-MOSFETs in cascode and differential amplifier circuits.

Scaling considerations for sub-90 nm split-gate flash memory cells

This paper presents a systematic study of the effect of source/drain (S/D) implant lateral straggle on the RF performance of the symmetric and asymmetric underlap double gate (UDG) MOSFET devices. The length of the underlap regions (Lun) on each side of the gate is a critical technology parameter in determining the performance of UDG-MOSFETs. However, the value of Lun is susceptible to variation due to S/D implant lateral diffusion. Therefore, it is critical to investigate the impact of S/D implant lateral straggle on the performance of UDG-MOSFETs. This paper shows that the improvement in the RF performance of the UDG-MOSFETs over the conventional DG-MOSFETs can be achieved by optimizing the S/D lateral straggle of the asymmetric UDG-MOSFETs. The RF performance study includes intrinsic capacitances and resistances, transport delay, inductance, and the cut-off frequency.

Analysis of Harmonic Distortion in UDG-MOSFETs

In this paper, the performance of dual-k spacer asymmetric underlap FinFET (DKAU-FinFET) is analyzed. The significance of using dual-k spacers is illustrated considering the parasitic outer fringing capacitance. The study also presents physical insights into inversion charge modulation by dual-k spacers in DKAU-FinFETs. In addition, the proposed device structure is analyzed for analog, RF, and digital circuit performances. Based on the performance analysis, the use of optimum inner high-k spacer thickness is proposed for reliable device performance.

Effect of Source/Drain Lateral Straggle on Distortion and Intrinsic Performance of Asymmetric Underlap DG-MOSFETs

A model including the presence and effect of discrete quantum energy levels and trap states in nanocrystals is proposed in order to describe the anomalous peaks observed in current-voltage characteristics of emerging Si quantum dot based floating gate flash memory cells. The model is employed to investigate the effect of energy levels in quantum dots with a size distribution in the range of 0 to 12 nm in explaining the charging dynamics and current versus time characteristics. The simulated results are in close agreement with the experimental results. It is speculated that the additional peaks observed in the experimental current versus voltage characteristics above threshold voltage are because of the filling up of nanocrystals with more than one electron into quantum levels, shifted to higher energy levels due to the increase in charging energy determined by self capacitance.

Physical Insights Into Electric Field Modulation in Dual-

This paper reports a systematic methodology to enhance the performance of germanium p-type tunnel FETs (Ge-pTFETs) using a p+ pocket implant at the source end of the channel and an underlap region at the drain end. The numerical device simulation results show that an optimized drain-underlap region reduces the off-state leakage current (IOFF) of 50-nm Ge-pTFETs to about 3.27 pA/μm without degrading the ON-current (ION), and a p+ pocket doping improves the ion of these devices to about 0.295 mA/μm without compromising IOFF. The analog and RF performances of the drain-underlapped Ge-pTFETs are investigated in terms of the drain current, transconductance, output resistance, intrinsic gain, cutoff frequency, and maximum frequency of oscillation for pocket-doping length varying from 0 to 6 nm. In addition, the influence of the pocket doping on the nonquasi-static performance is analyzed in terms of the gate-source and gate-drain capacitances, gate-drain resistance, and intrinsic delay time. Finally, the performance of the source-pocket drain-underlapped Ge-pTFETs in ICs is studied using a common source amplifier.

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This paper presents the results of a systematic theoretical investigation on the impact of gate height on the analog and radio-frequency (RF) performances of underlap-FinFET devices. The conventional underlap-FinFETs offer lower on current (I_on) and higher distributed channel resistance (R_ch). This paper shows that a higher gate height improves both I_on and R_ch due to higher gate side-wall fringing fields. In this paper, the various figure of merits (FOMs) for analog applications of the underlap-FinFETs such as drain current (Ids), transconductance (g_m), transconductance generation factor (g_m/I_ds), output resistance (R_o), and intrinsic gain (g_mR_o) are systematically analyzed for different values of gate height and reported. The RF FOMs studied include intrinsic capacitances (C_gs, C_gd) and resistances (R_gs, R_gd), transport delay (τ_m), cutoff frequency (f_T), and the transit frequency of maximum available power gain (f_MAX). This paper clearly demonstrates that the gate height is a critical technology parameter in improving the analog performance of underlap-FinFETs.