Binit Syamal

Influence of Channel and Gate Engineering on the Analog and RF Performance of DG MOSFETs

The design of analog and RF circuits in CMOS technology has become increasingly more difficult as device modeling faces new challenges in the deep-submicrometer regime and emerging circuit applications. In this paper, we investigate the influence of both channel and gate engineering on the analog and RF performances of double-gate (DG) MOSFETs for system-on-chip applications. The gate engineering technique used here is the dual-metal gate technology, and the channel engineering technique is the conventional halo doping process. For analog applications, importance is given to the subthreshold regime as CMOS circuits operated in this regime are very much attractive for ultralow-power high-gain performances. Gate- and channel-engineered devices show an increase of gain by 45% and 35%, respectively, compared with the single-metal DG MOSFET. The gate-engineered device shows an improvement of 21.6% and 20% in the case of fT and fMAX values, whereas the channel-engineered device exhibits a reduction of fT by 2.7% with nearly equal fMAX.

Subthreshold Analog/RF Performance Enhancement of Underlap DG FETs With High- K Spacer for Low Power Applications

This paper presents a systematic study of the subthreshold analog/RF performance for underlap double gate (UDG) NMOSFETs using high dielectric constant (k) spacers. The conventional UDG-NMOSFETs offer reduced short-channel effects along with improved subthreshold analog/RF performance at a cost of higher distributed channel resistance and low on current. In this paper, we show that these drawbacks can be alleviated effectively by using high-k spacers without any severe degradation in the subthreshold analog/RF performance. In order to show the improvement in the device performance, we have studied the effect of high-k spacers on different subthreshold analog figures of merit such as the transconductance, transconductance generation factor, output resistance, and the intrinsic gain for different values of k . Moreover, we have analyzed the RF performance as a function of intrinsic capacitance and resistance, transport delay, inductance, cutoff frequency, and the maximum oscillation frequency. In order to assess the gain bandwidth (GBW) product, the circuit implementation of the UDG-NMOSFETs with different high-k spacers was performed on a common source amplifier. Our results show an improvement in the GBW of about 38% for the devices with high- k spacers compared to its low- k counterpart.

Effect of single HALO doped channel in Tunnel FETs: A 2-D modeling study

Tunnel FETs has emerged as a promising candidate to replace the conventional CMOS technology in the near future owing to its sub-60 mV/dec subthreshold slope. In this paper we have explored the effects of asymmetric channel doping in Tunnel FET devices through extensive modeling and simulation approaches. A Halo doped pocket implantation at the source end is expected to decrease the width of the depletion region resulting in considerable increase in the device current. A compact surface potential model is developed based on the 2-D Poissons equation followed by the calculation of band energy. The effect of doping of the pocket implantation is studied that helps to optimize the level of HALO doping and thereby, the length of the doped region. The obtained results are compared with a device simulator Sentaurus TCAD and a good agreement is observed.

Performance and optimisation of dual material gate short channel BULK MOSFETs for analogue/mixed signal applications

The challenge of analogue operation of CMOS devices and its parameters is a very important study for future technologies. In this article, the performance of dual material gate bulk MOSFETs for analogue/mixed signal applications is explored. Moreover, the optimisation of the device is done based on the variation of length and work-function difference of the two gate metals. The effect of drain induced barrier lowering in this structure is studied in detail. Moreover the different analogue parameters such as transconductance (g m), output resistance (R o) tuning for high performance of the device are also investigated by extensive simulations.

Unified drain current model for independently driven double gate MOSFETs

A generic surface potential based current voltage (I–V) model for heavily doped asymmetric Double Gate MOSFET is presented. The model is derived from the 1-D Poisson equation with all the charge terms included and the channel potential is solved for the asymmetric operation of DG MOSFET based on the Newton Raphson Iterative method. A non charge sheet based drain current model based on the Pao-Sahs double integral method is formulated in terms of front and back gate surface potentials at the source and drain end. The model is able to clearly show the dependence of the front and back surface potentials and the drain current on the terminal voltages, gate oxide thicknesses, channel doping concentrations and the Silicon body thickness and a good agreement is observed with the 2-D numerical simulation results.

Noise performance of Gate engineered double gate MOSFETs for analog and RF applications

Due to their excellent scalability and better immunity to short channel effects, Double gate MOSFETs rule the CMOS applications era. However for channel lengths below 100nm, DG MOSFETs still show considerable threshold voltage roll off and to overcome this, gate engineering technique can be widely used. In this paper, we systematically investigate the analog/RF and Noise performance of Gate engineered DG MOSFETs for System-on-chip applications. A very good improvement in noise parameters such as power spectral density and Noise figure are observed in case of DMDG devices compared to its single metal counterpart.

Modeling of noise for p-channel DG-FinFETs

Abstract The noise performance of p-channel Double Gate FinFETs has been studied with varying structural parameters. The effects of mobility degradation due to velocity saturation, carrier heating and channel length modulation have been taken into consideration for an accurate modeling of noise. The dependence of mobility fluctuations on the inversion carrier density has been incorporated. This has been validated by the experimental results. The noise behavior of p-channel device has been compared to that of a corresponding n-channel device. It has been observed that noise in p-channel device is comparatively higher due to higher number of oxide-trap density in it. Further, it has been noted that with the same trap density in both p-channel and n-channel device, the flicker noise in the p-channel device is lower than that of the corresponding n-channel device.

RF parameter extraction of Bulk FinFET: A non quasi static approach

In this paper, we present a simple and accurate method to extract the parasitic as well as the intrinsic components of a Bulk FinFET device. Based on the Y- parameter data obtained from the 3-dimensional device simulator Sentaurus TCAD, the parasitic components are de-embedded and an accurate modeling based on the equivalent small signal circuit is presented to extract the intrinsic parameters. The non-quasi static effect is included and so the model predicts the Y parameter values accurately at high frequencies.

Modeling of flicker noise in n-channel FinFETs: Mobility fluctuations in the subthreshold region

In this work, the flicker noise in n-channel FinFETs has been modeled. The model has been developed by considering both mobility and carrier number fluctuations in the weak, moderate and strong inversion regions of operation of FinFETs. It has been demonstrated that mobility fluctuations cannot be neglected in FinFETs under the weak inversion region of its operation. For validation purpose, the model results have been verified with experimental data. Good agreement between the model results and experimental data has been observed.

An analytical drain current model for undoped 4-T asymmetric double gate MOSFETs

In this paper, we derive an analytical model of drain current for an Undoped 4-T asymmetric Double Gate MOSFET based on the solution of the 1-D Poissons equation. The equations are valid for both the subthreshold and superthreshold regime of operation. The current is formulated using the Pao-Sahs double integral method. The model can be used to study the effect of the different gate voltages, gate work functions and the oxide thickness of the front and back gate on the drain current of the undoped DG MOSFET. The results have been verified with a 2-D device simulator and a good agreement is obtained.