Samer Banna

Reducing damage to Si substrates during gate etching processes by synchronous plasma pulsing

Plasma oxidation of the c-Si substrate through a very thin gate oxide layer can be observed during HBr/O2/Ar based plasma overetch steps of gate etch processes. This phenomenon generates the so-called silicon recess in the channel and source/drain regions of the transistors. In this work, the authors compare the silicon recess generated by continuous wave HBr/O2/Ar plasmas and synchronous pulsed HBr/O2/Ar plasmas. Thin SiO2 layers are exposed to continuous and pulsed HBr/O2/Ar plasmas, reproducing the overetch process conditions of a typical gate etch process. Using in situ ellipsometry and angle resolved X-ray photoelectron spectroscopy, the authors demonstrate that the oxidized layer which leads to silicon recess can be reduced from 4 to 0.8 nm by pulsing the plasma in synchronous mode.

Effect of simultaneous source and bias pulsing in inductively coupled plasma etching

Pulsed rf plasmas show promise to overcome challenges for plasma etching at future technological nodes. In pulsed plasmas, it is important to characterize the transient phenomena to optimize plasma processing of materials. In particular, it is important to evaluate the effect of the ion energy and angular distribution (IEAD) functions during pulsing on etching of nanoscale features. In this work, the impact of simultaneous pulsing of both source and bias in an inductively coupled plasma on plasma characteristics and feature profile evolution is discussed using results from a two-dimensional reactor scale plasma model coupled to a Monte Carlo based feature profile model. Results are discussed for an Ar∕Cl2 gas mixture which is typically used for poly-Si etching. The consequences of duty cycle, pulse shape, and the phase lag between source and bias power pulses on discharge characteristics, IEADs to the wafer, and feature profile evolution are discussed. The low plasma density during the initial period of t...

Silicon recess minimization during gate patterning using synchronous plasma pulsing

With the emergence of new semiconductor devices and architectures, there is a real need to limit plasma induced damage. This study clearly demonstrates the capability of pulsed plasma technology to minimize plasma induced silicon oxidation that leads to the silicon recess phenomenon during polysilicon gate patterning. Indeed, the authors show that by pulsing optimized continuous wave overetch plasma conditions using HBr/He/O2 plasmas, the silicon recess is reduced from 0.6 to 0.2u2009nm, while the gate profiles are maintained anisotropic. Synchronous pulsed plasmas open new paths to pattern complex stacks of ultrathin materials without surface damage.

Synchronous Pulse Plasma Operation upon Source and Bias Radio Frequencys for Inductively Coupled Plasma for Highly Reliable Gate Etching Technology

Synchronous pulse operation upon both source and bias RFs for inductively coupled plasma (ICP) etching system, having both dynamic matching networks and RF frequency-sweeping to ensure the lowest RF reflected power, is introduced for the first time. A superior performance of synchronous pulse operation to conventional continuous wave (cw) as well as source pulse operations is confirmed through plasma diagnostics by using Langmuir probe, plasma simulation by using hybrid plasma equipment model (HPEM) and etching performance. Significant reduction of RF power reflection during pulse operation as well as improvement of 35 nm gate critical dimension (CD) uniformity for sub-50 nm dynamic random access memory (DRAM) are achieved by adapting synchronous pulse plasma etching technology. It is definitely expected that synchronous pulse plasma system would have a great ability from a perspective of robustness on fabrication site, excellent gate CD controllability and minimization of plasma induced damage (PID) related device performance degradation.

Towards new plasma technologies for 22nm gate etch processes and beyond

Since more than 30 years, CW plasmas have been used in the microelectronics industry to pattern complex stacks of materials involved in Integrated Circuit technologies. Even if miniaturization challenges have been successfully addressed thanks to plasma patterning technologies, several fundamental limitations of the plasmas remain and are limiting our ability to shrink further the device dimensions. In this work, we analyze the capabilities of synchronized pulsed ICP technologies and their potential benefits for front end etch process performance. The impact of duty cycle and frequency on the ion energy distribution function and plasma chemistry is analyzed. Our results show that decreasing the duty cycle in ICP plasmas generates less fragmentation of the feed gas stock molecules compared to CW plasmas, leading in final to a decrease of the radical density in the plasma. On a process point of view, we have studied the etching of ultra-thin layers (SiO2, HfO2,SiN spacer) involved in front end processes and investigated what synchronized pulsed plasmas could bring to substrate damage and selectivity issues.

Characterization of silicon etching in synchronized pulsed plasma

Pulsed plasmas have been proposed many years ago by research labs and have shown a great potential for etch process improvement. Nevertheless, they have been introduced in manufacturing only recently and the exact characteristics of pulsed plasmas in industrial scale reactors are hardly known. In this paper, we have characterized silicon etching in pulsed HBr/O2 plasmas using advanced plasma diagnostics (mass spectrometry and ion flux probe) in a 300 mm industrial reactor. We show that pulsing the plasma at low duty cycle reduces the gas molecules dissociation and plasma temperature, as well as the flux of energetic ions to the wafer. The ions during silicon etching are mostly silicon-containing ions that are heavier at low duty cycle. Silicon patterns etched using pulsed plasmas present improved profiles, which is attributed to more uniform passivation layers at low duty cycle.