Valentin N. Todorow

Inductively Coupled Pulsed Plasmas in the Presence of Synchronous Pulsed Substrate Bias for Robust, Reliable, and Fine Conductor Etching

Inductively coupled pulsed plasmas in the presence of synchronous pulsed substrate bias are characterized in a commercial plasma etching reactor for conductor etching. The synchronous pulsed plasma characteristics are evaluated through the following: 1) Ar-based Langmuir probe diagnostics; 2) Ar/Cl2 plasma modeling utilizing the hybrid plasma equipment model and the Monte Carlo feature model for the investigation of feature profile evolutions; 3) basic etching characteristics such as average etch rate and uniformity; 4) sub-50-nm Dynamic Random Access Memory (DRAM) basic etching performance and profile control; and 5) charge damage evaluation. It is demonstrated that one can control the etching uniformity and profile in advanced gate etching, and reduce the leakage current by varying the synchronous pulsed plasma parameters. Moreover, it is shown that synchronous pulsing has the promise of significantly reducing the electron shading effects compared with source pulsing mode and continuous-wave mode. The synchronous pulsed plasma paves the way to a wider window of operating conditions, which allows new plasma etching processes to address the large number of challenges emerging in the 45-nm and below technologies.

Synchronous Pulse Plasma Operation upon Source and Bias Radio Frequencys for Inductively Coupled Plasma for Highly Reliable Gate Etching Technology

Synchronous pulse operation upon both source and bias RFs for inductively coupled plasma (ICP) etching system, having both dynamic matching networks and RF frequency-sweeping to ensure the lowest RF reflected power, is introduced for the first time. A superior performance of synchronous pulse operation to conventional continuous wave (cw) as well as source pulse operations is confirmed through plasma diagnostics by using Langmuir probe, plasma simulation by using hybrid plasma equipment model (HPEM) and etching performance. Significant reduction of RF power reflection during pulse operation as well as improvement of 35 nm gate critical dimension (CD) uniformity for sub-50 nm dynamic random access memory (DRAM) are achieved by adapting synchronous pulse plasma etching technology. It is definitely expected that synchronous pulse plasma system would have a great ability from a perspective of robustness on fabrication site, excellent gate CD controllability and minimization of plasma induced damage (PID) related device performance degradation.

Impact of Phase Shifted Coil Currents on Plasma Uniformity

Plasma etching at sub-3x-nm nodes requires inductively coupled plasma (ICP) reactors to work within tight uniformity constraints. The characteristic donut shape of the ICPs is, however, visible on the wafer in a 20-60 mTorr range due to reduced plasma diffusion. Phase shifting of the coil currents in an ICP source has been used to improve plasma uniformity. Images of plasma properties with and without phase shift of coil currents are presented.