Samuel Evain

Generalized parity-check matrices for SEC-DED codes with fixed parity

Hsiao and extended Hamming parity-check matrices can be used to define systematic linear block codes for Single Error Correction-Double Error Detection (SEC-DED). Their fixed code word parity enables the construction of low density parity-check matrices and fast hardware implementations. Fixed code word parity is enabled by an all-one row in extended Hamming parity-check matrices or by the constraint that the modulo-2 sum of all rows is equal to the all-zero vector in Hsiao parity-check matrices. In this paper, we show that these two constraints are particular instantiations of a more general constraint which involves an arbitrary number of rows in the parity-check matrix. As a consequence, sparser parity-check matrices with faster hardware implementations can be found. Moreover, special instantiations of these matrices enable the detection of all triple-bit and quadruple-bit burst errors.

System-level hardware-based protection of memories against soft-errors

We present a hardware-based approach to improve the resilience of a computer system against the errors occurred in the main memory with the help of error detecting and correcting (EDAC) codes. Checksums are placed in the same type of memory locations and addressed in the same way as normal data. Consequently, the checksums are accessible from the exterior of the main memory just as normal data and this enables implicit fault-tolerance for interconnection and solid-state secondary storage sub-systems. A small hardware module is used to manage the sequential retrieval of checksums each time the integrity of the data accessed by the processor sub-system needs to be verified. The proposed approach has the following properties: (a) it is cost efficient since it can be used with simple storage and interconnection sub-systems that do not possess any inherent EDAC mechanism, (b) it allows on-line modifications of the memory protection levels, and (c) no modification of the application software is required.

Error prediction based on concurrent self-test and reduced slack time

Small circuit defects occurred during manufacturing and/or enhanced/induced by various aging mechanisms represent a serious challenge in advanced scaled CMOS technologies. These defects initially manifest as small delay faults that may evolve in time and exceed the slack time in the clock cycle period. Periodic tests performed with reduced slack time provide a low-cost solution that allows to predict failures induced by slowly evolving delay faults. Unfortunately, such tests have limited fault coverage and fault detection latency. Here, we introduce a way to complement or completely replace the periodic testing with reduced slack time. Delay control structures are proposed to enable arbitrarily small parts of the monitored component to switch fast between a normal operating mode and a degraded mode characterized by a smaller slack time. Only two or three additional transistors are needed for each flip-flop in the monitored logic. Micro-architectural support for a concurrent self-test of pipelined logic that takes benefit of the introduced degraded mode is presented as well. Test stimuli are produced on the fly by the last two valid operations executed before each stall cycle. Test result evaluation is facilitated by the replication of the last valid operation during a stall cycle. Protection against transient faults can be achieved if each operation is replicated via stall cycle insertion.

Programmable extended SEC-DED codes for memory errors

Redundant memory columns are an essential ingredient of memory design for yield and reliability. They are used either as spare columns for the replacement of completely defective regular columns or to store check-bits for error detection and correction codes. Column replacement allows to mask isolated malfunctioning storage cells as well. Unfortunately, the number of columns with defective storage cells that can be masked in this way cannot exceed the number of spare columns which is usually quite low. Here, we propose a way to increase the capacity of masking memory columns with isolated defective storage cells using spare memory columns. For this purpose, single error correction and double error detection (SEC-DED) codes already available for the protection against soft errors are extended such that all double-bit errors which affect a fixed sub-set of bit positions in the code words can be corrected. The cardinality of this sub-set is significantly higher than the number of spare columns. A bit-swapper is employed to map the bit positions that are protected by the extended SEC-DED code against double-bit errors to the memory columns with defective storage cells. In this way, single-bit soft-errors affecting any bit position can be corrected simultaneously with single-bit hard errors induced by any sub-set of memory columns. The bit-swapper can be dynamically reconfigured based on status information that designates the memory columns with defective storage cells. This facilitates the integration into built-in self-repair (BISR) schemes.

OMTDR based integrated cable health monitoring system SmartCo: An embedded reflectometry system to ensure harness auto-test

This paper presents the first embedded health monitoring system able to analyze network/harness health using OMTDR (Orthogonal Multi-tone Time Domain Reflectometry) technology. OMTDR is a suitable candidate for on-line diagnosis as it permits interference avoidance by bandwidth control. Thanks to OMTDRs communication capability, network analysis as well as sensors intelligence can be easily distributed without any impact on network traffic. Complex network can be analyzed and fault location ambiguity can be solved thanks to distributed analysis. This enables to aggregate diagnosis information from several sensors and make a high level decision. Even for a simple network, OMTDR obtains a better fault location accuracy by combining different location data. In this paper, we analyze the benefit of integrating OMTDR into the harness. The demonstrator embeds both real time distributed wire diagnosis and sensor communication in 2 standard aerospace connectors. Thanks to this intelligence and capability added into commercial connectors, we call this innovative proposed solution: SmartCo for Smart-Connector. Hardware, software and demonstrator interface are presented in details.

Scan design with shadow flip-flops for low performance overhead and concurrent delay fault detection

This paper presents new scan solutions with low latency overhead and on-line monitoring support. Shadow flip-flops with scan design are associated to system flip-flops in order to (a) provide concurrent delay fault detection and (b) avoid the scan chain insertion of system flip-flops. A mixed scan architecture is proposed which involves flip-flops with shadow scan design at the end of timing-critical paths and flip-flops with standard scan at non-critical locations. In order to preserve system controllability during test, system flip-flops with shadow scan can be set in scan mode and selectively reset before switching to capture mode. It is shown that shadow scan design with asynchronous set and reset may have a lower latency overhead than standard scan design. A shadow scan solution is proposed which, in addition to concurrent delay fault detection, provides simultaneous scan and capture capability.

Error Correction Schemes with Erasure Information for Fast Memories

Two error correction schemes are proposed for word-oriented binary memories that can be affected by erasures, i.e. errors with known location but unknown value. The erasures considered here are due to the drifting of the electrical parameter used to encode information outside the normal ranges associated to a logic 0 or a logic 1 value. For example, a dielectric breakdown in a magnetic memory cell may reduce its electrical resistance sensibly below the levels which correspond to logic 0 and logic 1 values stored in healthy memory cells. Such deviations can be sensed during memory read operations and the acquired information can be used to boost the correction capability of an error-correcting code (ECC). The proposed schemes enable the correction of double-bit errors based on the combination of erasure information with single-bit error correction and double-bit error detection (SEC-DED) codes or shortened (SEC) codes. The correction of single-bit errors is always guaranteed. Ways to increase the number of double-bit and triple-bit errors that can be detected by shortened SEC and SEC-DED codes are considered in order to augment the error correction capability of the proposed solutions.

Error-correction schemes with erasure information for fast memories

Two error correction schemes are proposed for binary memories that can be affected by erasures, i.e. errors with known location but unknown value. The erasures considered here are due to the drifting of the electrical parameter used to encode information outside the normal ranges associated to a logic 0 or a logic 1 value. For example, a dielectric breakdown in a magnetic memory cell may reduce its electrical resistance sensibly below the levels which correspond to logic 0 and logic 1 values stored in healthy memory cells. Such deviations can be sensed during memory read operations and the acquired information can be used to boost the fault masking capacity of an error-correcting code. Here, we investigate the use of erasure information to enable double-bit error correction with the help of single-bit error correction and double-bit error detection codes or shortened single-bit error correction codes.

Flip-Flop Selection for In-Situ Slack-Time Monitoring based on the Activation Probability of Timing-Critical Paths

In-situ slack-time monitoring may be used to enable ambitious power management policies under circuit wear-out and dynamic temperature and supply voltage variations. Given a limited hardware budget, it becomes crucial to be able to select the most appropriate places for in-situ slack-time monitoring. Here, two metrics are proposed to guide the selection of a set of flip-flops (FFs) for in-situ slack-time monitoring. The goal of these metrics is to maximize the ratio of clock cycles with at least one monitor activated and the number of activated monitors per clock cycle. The activation probability of a monitor is evaluated with the help of timing simulations as the probability that signals are propagated along the monitored timing-critical paths. It is shown that in-situ slack-time monitors with detection windows correlated to the minimum slack-time of the monitored timing-critical paths can provide better results than similar monitors with a constant detection window for the same impact on the circuit latency.

Memory reliability improvements based on maximized error-correcting codes

Error-correcting codes (ECC) offer an efficient way to improve the reliability and yield of memory subsystems. ECC-based protection is usually provided on a memory word basis such that the number of data-bits in a codeword corresponds to the amount of information that can be transferred during a single memory access operation. Consequently, the codeword length is not the maximum allowed by a certain check-bit number since the number of data-bits is constrained by the width of the memory data interface. This work investigates the additional error correction opportunities offered by the absence of a perfect match between the numbers of data-bits and check-bits in some of the most used ECCs. A method is proposed for the selection of multiple-bit errors which can become correctable with a minimal impact on decoder latency. Reliability improvements are evaluated for memories in which all errors affecting the same number of bits in a codeword are equally probable. It is shown that the application of the proposed methods to standard double-bit ECCs can improve the mean-time-to-failure (MTTF) of memories with up to 100%.