Valentin Gherman

Efficient pattern mapping for deterministic logic BIST

Deterministic logic BIST (DLBIST) is an attractive test strategy, since it combines advantages of deterministic external testing and pseudo-random LBIST. Unfortunately, previously published DLBIST methods are unsuited for large ICs, since computing time and memory consumption of the DLBIST synthesis algorithms increase exponentially, or at least cubically, with the circuit size. In this paper, we propose a novel DLBIST synthesis procedure that has nearly linear complexity in terms of both computing time and memory consumption. The new algorithms are based on binary decision diagrams (BDDs). We demonstrate the efficiency of the new algorithms for industrial designs up to 2M gates.

Deterministic Logic BIST for Transition Fault Testing

BIST is an attractive approach to detect delay faults due to its inherent support for at-speed test. Deterministic logic BIST (DLBIST) is a technique which was successfully applied to stuck-at fault testing. As delay faults have lower random pattern testability than stuck-at faults, the need for DLBIST schemes is increased. Nevertheless, an extension to delay fault testing is not trivial, since this necessitates the application of pattern pairs. Consequently, delay fault testing is expected to require a larger mapping effort and logic overhead than stuck-at fault testing. In this paper, we consider the so-called transition fault model, which is widely used for complexity reasons. We present an extension of a DLBIST scheme for transition fault testing. Functional justification is used to generate the required pattern pairs. The efficiency of the extended scheme is investigated by using industrial benchmark circuits.

Implementing a scheme for external deterministic self-test

A method for test resource partitioning is introduced which keeps the design-for-test logic test set independent and moves the test pattern dependent information to an external, programmable chip. The scheme includes a new decompression scheme for a fast and efficient communication between the external test chip and the circuit under test. The hardware costs on chip are significantly lower compared with a deterministic BIST scheme while the test application time is still in the same range. The proposed scheme is fully programmable, flexible and can be reused at board level for testing in the field.

Programmable extended SEC-DED codes for memory errors

Redundant memory columns are an essential ingredient of memory design for yield and reliability. They are used either as spare columns for the replacement of completely defective regular columns or to store check-bits for error detection and correction codes. Column replacement allows to mask isolated malfunctioning storage cells as well. Unfortunately, the number of columns with defective storage cells that can be masked in this way cannot exceed the number of spare columns which is usually quite low. Here, we propose a way to increase the capacity of masking memory columns with isolated defective storage cells using spare memory columns. For this purpose, single error correction and double error detection (SEC-DED) codes already available for the protection against soft errors are extended such that all double-bit errors which affect a fixed sub-set of bit positions in the code words can be corrected. The cardinality of this sub-set is significantly higher than the number of spare columns. A bit-swapper is employed to map the bit positions that are protected by the extended SEC-DED code against double-bit errors to the memory columns with defective storage cells. In this way, single-bit soft-errors affecting any bit position can be corrected simultaneously with single-bit hard errors induced by any sub-set of memory columns. The bit-swapper can be dynamically reconfigured based on status information that designates the memory columns with defective storage cells. This facilitates the integration into built-in self-repair (BISR) schemes.

Scan design with shadow flip-flops for low performance overhead and concurrent delay fault detection

This paper presents new scan solutions with low latency overhead and on-line monitoring support. Shadow flip-flops with scan design are associated to system flip-flops in order to (a) provide concurrent delay fault detection and (b) avoid the scan chain insertion of system flip-flops. A mixed scan architecture is proposed which involves flip-flops with shadow scan design at the end of timing-critical paths and flip-flops with standard scan at non-critical locations. In order to preserve system controllability during test, system flip-flops with shadow scan can be set in scan mode and selectively reset before switching to capture mode. It is shown that shadow scan design with asynchronous set and reset may have a lower latency overhead than standard scan design. A shadow scan solution is proposed which, in addition to concurrent delay fault detection, provides simultaneous scan and capture capability.

Error Correction Schemes with Erasure Information for Fast Memories

Two error correction schemes are proposed for word-oriented binary memories that can be affected by erasures, i.e. errors with known location but unknown value. The erasures considered here are due to the drifting of the electrical parameter used to encode information outside the normal ranges associated to a logic 0 or a logic 1 value. For example, a dielectric breakdown in a magnetic memory cell may reduce its electrical resistance sensibly below the levels which correspond to logic 0 and logic 1 values stored in healthy memory cells. Such deviations can be sensed during memory read operations and the acquired information can be used to boost the correction capability of an error-correcting code (ECC). The proposed schemes enable the correction of double-bit errors based on the combination of erasure information with single-bit error correction and double-bit error detection (SEC-DED) codes or shortened (SEC) codes. The correction of single-bit errors is always guaranteed. Ways to increase the number of double-bit and triple-bit errors that can be detected by shortened SEC and SEC-DED codes are considered in order to augment the error correction capability of the proposed solutions.

Error-correction schemes with erasure information for fast memories

Two error correction schemes are proposed for binary memories that can be affected by erasures, i.e. errors with known location but unknown value. The erasures considered here are due to the drifting of the electrical parameter used to encode information outside the normal ranges associated to a logic 0 or a logic 1 value. For example, a dielectric breakdown in a magnetic memory cell may reduce its electrical resistance sensibly below the levels which correspond to logic 0 and logic 1 values stored in healthy memory cells. Such deviations can be sensed during memory read operations and the acquired information can be used to boost the fault masking capacity of an error-correcting code. Here, we investigate the use of erasure information to enable double-bit error correction with the help of single-bit error correction and double-bit error detection codes or shortened single-bit error correction codes.

Flip-Flop Selection for In-Situ Slack-Time Monitoring based on the Activation Probability of Timing-Critical Paths

In-situ slack-time monitoring may be used to enable ambitious power management policies under circuit wear-out and dynamic temperature and supply voltage variations. Given a limited hardware budget, it becomes crucial to be able to select the most appropriate places for in-situ slack-time monitoring. Here, two metrics are proposed to guide the selection of a set of flip-flops (FFs) for in-situ slack-time monitoring. The goal of these metrics is to maximize the ratio of clock cycles with at least one monitor activated and the number of activated monitors per clock cycle. The activation probability of a monitor is evaluated with the help of timing simulations as the probability that signals are propagated along the monitored timing-critical paths. It is shown that in-situ slack-time monitors with detection windows correlated to the minimum slack-time of the monitored timing-critical paths can provide better results than similar monitors with a constant detection window for the same impact on the circuit latency.

Memory reliability improvements based on maximized error-correcting codes

Error-correcting codes (ECC) offer an efficient way to improve the reliability and yield of memory subsystems. ECC-based protection is usually provided on a memory word basis such that the number of data-bits in a codeword corresponds to the amount of information that can be transferred during a single memory access operation. Consequently, the codeword length is not the maximum allowed by a certain check-bit number since the number of data-bits is constrained by the width of the memory data interface. This work investigates the additional error correction opportunities offered by the absence of a perfect match between the numbers of data-bits and check-bits in some of the most used ECCs. A method is proposed for the selection of multiple-bit errors which can become correctable with a minimal impact on decoder latency. Reliability improvements are evaluated for memories in which all errors affecting the same number of bits in a codeword are equally probable. It is shown that the application of the proposed methods to standard double-bit ECCs can improve the mean-time-to-failure (MTTF) of memories with up to 100%.

Improvement of the tolerated raw bit error rate in NAND flash-based SSDs with the help of embedded statistics

Solid-state drives (SSDs) based on NAND flash memories provide an attractive storage solution as they are faster and less power hungry than traditional hard-disc drives (HDDs). Aggressive storage density improvements in flash memories enabled reductions of the cost per gigabit but also caused reliability degradations. A recent large-scale study revealed that the uncorrectable bit error rates (UBER) in data center SSDs may fall far below the JEDEC standard recommendations. Here, a technique is proposed to improve the tolerated raw bit error rate (RBER) based on the observation that (a) a small SSD ratio may have a much higher RBER than the rest and (b) the RBER is dominated by the retention error rate. Instead of employing stronger but costly error-correcting codes a statistical approach is used to estimate the remaining retention time, i.e., the reliable data storage time, of flash memory pages. This estimation can be performed each time a memory page is read based on the number of detected retention errors and the elapsed time since data was programmed. The fact that the estimated remaining retention time is smaller than a maximum time interval before the next read operation is an indication that data needs to be refreshed. It is estimated that the tolerated RBER can be increased by more than a decade over a storage period of 3 years if the stored data are verified on a monthly basis and refreshed only if necessary. The proposed technique has the ability to adapt the average time between refresh operations to the actual RBER. This enables performance overhead reductions with factors between 8x and 12x as compared to systematic refresh schemes.