Yannick Bonhomme

A gated clock scheme for low power scan testing of logic ICs or embedded cores

Test power is now a big concern in large system-on-chip designs. In this paper, we present a novel approach for minimizing power consumption during scan testing of integrated circuits or embedded cores. The proposed low power technique is based on a gated clock scheme for the scan path and the clock tree feeding the scan path. The idea is to reduce the clock rate on scan cells during shift operations without increasing the test time. Numerous advantages can be found in applying such a technique.

Power driven chaining of flip-flops in scan architectures

Power consumption during scan testing is becoming a primary concern. In this paper, we present a novel approach for scan cell ordering which significantly reduces the power consumed during scan testing. The proposed approach is based on the use of a two-step heuristic procedure that can be exploited by any chip layout program during scan flip-flops placement and routing. The proposed approach works for any conventional scan design and offers numerous advantages compared with existing low power scan techniques. Reductions of average and peak power consumption during scan testing are up to 58% and 24% respectively for experimented ISCAS benchmark circuits.

Test power: a big issue in large SOC designs

Test power relates to the power consumed during test of integrated circuits or embedded cores. Test power is now a big concern in large System-on-Chip designs. In this work, we propose to shortly review the state-of-the-art in this domain. We first survey the recent approaches proposed for minimizing test power. Next, we propose some interesting directions for the development of new low power testing techniques by enumerating the relevant criteria that have to be satisfied.

Generalized parity-check matrices for SEC-DED codes with fixed parity

Hsiao and extended Hamming parity-check matrices can be used to define systematic linear block codes for Single Error Correction-Double Error Detection (SEC-DED). Their fixed code word parity enables the construction of low density parity-check matrices and fast hardware implementations. Fixed code word parity is enabled by an all-one row in extended Hamming parity-check matrices or by the constraint that the modulo-2 sum of all rows is equal to the all-zero vector in Hsiao parity-check matrices. In this paper, we show that these two constraints are particular instantiations of a more general constraint which involves an arbitrary number of rows in the parity-check matrix. As a consequence, sparser parity-check matrices with faster hardware implementations can be found. Moreover, special instantiations of these matrices enable the detection of all triple-bit and quadruple-bit burst errors.

System-level hardware-based protection of memories against soft-errors

We present a hardware-based approach to improve the resilience of a computer system against the errors occurred in the main memory with the help of error detecting and correcting (EDAC) codes. Checksums are placed in the same type of memory locations and addressed in the same way as normal data. Consequently, the checksums are accessible from the exterior of the main memory just as normal data and this enables implicit fault-tolerance for interconnection and solid-state secondary storage sub-systems. A small hardware module is used to manage the sequential retrieval of checksums each time the integrity of the data accessed by the processor sub-system needs to be verified. The proposed approach has the following properties: (a) it is cost efficient since it can be used with simple storage and interconnection sub-systems that do not possess any inherent EDAC mechanism, (b) it allows on-line modifications of the memory protection levels, and (c) no modification of the application software is required.

A gated clock scheme for low power scan-based BIST

Presents a new low power scan-based BIST technique which can reduce the switching activity during test operation. The proposed low power/energy technique is based on a gated clock scheme for the scan path and the clock tree feeding the scan path.

Error prediction based on concurrent self-test and reduced slack time

Small circuit defects occurred during manufacturing and/or enhanced/induced by various aging mechanisms represent a serious challenge in advanced scaled CMOS technologies. These defects initially manifest as small delay faults that may evolve in time and exceed the slack time in the clock cycle period. Periodic tests performed with reduced slack time provide a low-cost solution that allows to predict failures induced by slowly evolving delay faults. Unfortunately, such tests have limited fault coverage and fault detection latency. Here, we introduce a way to complement or completely replace the periodic testing with reduced slack time. Delay control structures are proposed to enable arbitrarily small parts of the monitored component to switch fast between a normal operating mode and a degraded mode characterized by a smaller slack time. Only two or three additional transistors are needed for each flip-flop in the monitored logic. Micro-architectural support for a concurrent self-test of pipelined logic that takes benefit of the introduced degraded mode is presented as well. Test stimuli are produced on the fly by the last two valid operations executed before each stall cycle. Test result evaluation is facilitated by the replication of the last valid operation during a stall cycle. Protection against transient faults can be achieved if each operation is replicated via stall cycle insertion.

A Gated Clock Scheme for Low Power Testing of Logic Cores

Test power is now a big concern in large core-based systems. In this paper, we present a general approach for minimizing power consumption during test of integrated circuits or embedded cores. The proposed low power/energy technique is based on a gated clock scheme that can be used in a test-per-scan or a test-per-clock environment. The idea is to reduce the clock rate on the scan path (test-per-scan) or the test pattern generator (test-per-clock) without increasing the test time. Numerous advantages can be found in applying such a technique.

Programmable extended SEC-DED codes for memory errors

Redundant memory columns are an essential ingredient of memory design for yield and reliability. They are used either as spare columns for the replacement of completely defective regular columns or to store check-bits for error detection and correction codes. Column replacement allows to mask isolated malfunctioning storage cells as well. Unfortunately, the number of columns with defective storage cells that can be masked in this way cannot exceed the number of spare columns which is usually quite low. Here, we propose a way to increase the capacity of masking memory columns with isolated defective storage cells using spare memory columns. For this purpose, single error correction and double error detection (SEC-DED) codes already available for the protection against soft errors are extended such that all double-bit errors which affect a fixed sub-set of bit positions in the code words can be corrected. The cardinality of this sub-set is significantly higher than the number of spare columns. A bit-swapper is employed to map the bit positions that are protected by the extended SEC-DED code against double-bit errors to the memory columns with defective storage cells. In this way, single-bit soft-errors affecting any bit position can be corrected simultaneously with single-bit hard errors induced by any sub-set of memory columns. The bit-swapper can be dynamically reconfigured based on status information that designates the memory columns with defective storage cells. This facilitates the integration into built-in self-repair (BISR) schemes.

OMTDR based integrated cable health monitoring system SmartCo: An embedded reflectometry system to ensure harness auto-test

This paper presents the first embedded health monitoring system able to analyze network/harness health using OMTDR (Orthogonal Multi-tone Time Domain Reflectometry) technology. OMTDR is a suitable candidate for on-line diagnosis as it permits interference avoidance by bandwidth control. Thanks to OMTDRs communication capability, network analysis as well as sensors intelligence can be easily distributed without any impact on network traffic. Complex network can be analyzed and fault location ambiguity can be solved thanks to distributed analysis. This enables to aggregate diagnosis information from several sensors and make a high level decision. Even for a simple network, OMTDR obtains a better fault location accuracy by combining different location data. In this paper, we analyze the benefit of integrating OMTDR into the harness. The demonstrator embeds both real time distributed wire diagnosis and sensor communication in 2 standard aerospace connectors. Thanks to this intelligence and capability added into commercial connectors, we call this innovative proposed solution: SmartCo for Smart-Connector. Hardware, software and demonstrator interface are presented in details.