Sanae Ito

Improvement of Drive Current in Bulk-FinFET using Full 3D Process/Device Simulations

We discussed the optimization of structure and doping profile of bulk-FinFETs by using 3D process and device simulations. The channel profile was determined so as to realize higher drive current as well as lower punch-through current. The analysis of stress field for bulk-FinFETs and SOI-FinFETs revealed that the channel stress induced by a stress liner (SL) in the bulk-FinFET is larger than that for the SOI-FinFET. In addition, we applied a raised source/drain (RSD) structure to the bulk-FinFETs and optimized doping profile in the RSD region. The combination of stress liner and RSD structure is found to be efficient for improving drive current of a bulk-FinFET

A FinFET design based on three-dimensional process and device simulations

In this paper, a practical design method of a FinFET is presented with :in example of a scaled DRAM device. The electric properties of the FinFET are analyzed by means of three-dimensional process and device simulations. The analysis reveals that the short channel effects depend strongly on not only the thickness but also the taper angle of the silicon pillar. The device is optimized successfully assuming the tapered shape for the silicon pillar. The simulated characteristics (0.1fA off-leak current and 62/spl mu/A drive current per unit cell @ 85C) well agree with experimental results.

Ion implantation as insoluble treatment for resist stacking process

With regard to the resist stacking process, it was proposed that the implantation of ions whose acceleration voltage was below 50 kV could make the lower-layer resist insoluble for the upper-layer resist patterning process. But the lower-layer resist pattern was observed to be peeled off in a pattern. In another type of the pattern whose lower-layer pattern was fastened by the upper-layer pattern, there were caves in the bottom of the lower-layer resist pattern. From the calculation of the projected range of the ions, it was found that the ions cannot reach the bottom of the lower-layer resist pattern, so that the bottom of the lower-layer resist was not hardened. The peeling-off was due to the dissolution of the bottom in the lower-layer resist during the development of the upper-layer resist pattern. When the acceleration voltage of the implanted ions is set so that the projected range of the ions is larger than the resist thickness, the lower-layer resist can be made effectively insoluble for the upper-layer resist patterning process. The ion implanted pattern can be used as the etching mask. Moreover, the ions can be prevented from penetrating the film to be etched by adjusting the acceleration voltage.

Statistical fluctuation analysis by Monte Carlo ion implantation method

This paper shows a new statistical fluctuation analysis method by Monte Carlo ion implantation and investigates Vt fluctuations due to statistical variation of dopant profile by 3D process-device simulation system. This method is very useful to analyze a statistical fluctuation in sub-100 nm MOSFETs efficiently.

Ion implantation as insoluble treatment for resist-stacking process

With regard to the resist-stacking process, it was proposed that the implantation of ions whose acceleration voltage was below 50 kV could make the lower-layer resist insoluble for the upper-layer resist-patterning process. However, the lower-layer resist pattern is observed to be removed after the upper-layer resist patterning in a pattern. In another type of a pattern, there are caves in the bottom of the lower-layer resist pattern after the upper-layer resist patterning. From the calculation of the projected range of the ions, it is found that the ions cannot reach the bottom of the lower-layer resist pattern, and therefore the bottom of the lower-layer resist is not hardened. The removal is due to the dissolution of the bottom in the lower-layer resist during the development of the upper-layer resist pattern. When the acceleration voltage of the implanted ions is set so that the projected range of the ions is larger than the resist thickness, the lower-layer resist can be made effectively insoluble for the upper-layer resist-patterning process. The ion-implanted pattern can be used as the etching mask. Moreover, the ions can be prevented from penetrating the film to be etched by adjusting the thicknesses of stacked antireflective coating.

Modeling of NBTI Degradation for SiON pMOSFET

For SiO2 pMOSFETs, the reaction diffusion model is well used to describe the NBTI degradation theoretically and the Ogawa model for hole trap generation is known exper imentally. However, there is not a good model of NBTI degradation for SiON devices. In this paper, we propose a nitrogen dependent hole trap generation model by extending these two models and present the NBTI degradation model for SiON pMOSFETs.