Takahisa Kanemura

Improvement of Drive Current in Bulk-FinFET using Full 3D Process/Device Simulations

We discussed the optimization of structure and doping profile of bulk-FinFETs by using 3D process and device simulations. The channel profile was determined so as to realize higher drive current as well as lower punch-through current. The analysis of stress field for bulk-FinFETs and SOI-FinFETs revealed that the channel stress induced by a stress liner (SL) in the bulk-FinFET is larger than that for the SOI-FinFET. In addition, we applied a raised source/drain (RSD) structure to the bulk-FinFETs and optimized doping profile in the RSD region. The combination of stress liner and RSD structure is found to be efficient for improving drive current of a bulk-FinFET

FinFET Process and Integration Technology for High Performance LSI in 22 nm node and beyond

This paper discusses the key FinFET process and integration technologies to achieve high performance LSI. Firstly, side wall pattern transfer technique is introduced to realize an aggressively scaled down FinFET with 10 nm Fin width (Wfin) and 15 nm gate length (Lg). Next, dopant segregation (DS) Schottky technique is demonstrated to enhance the FinFET performance. Drive current of 960 muA/mum for DS Schottky nFinFET with Lg = 15 nm at Ioff = 100 nA/mum and Vd= 1.0 V is achieved. And then, FinFET SRAM is fabricated and studied in the view of static noise margin (SNM). SNM of 122 mV is obtained in the cell with Wfin = 15 nm and Lg = 20 nm at Vd = 0.6 V. Also, fin height tuning technique is proposed so that SRAM operation can be optimized without area penalty. Finally, integration scheme of planar FET and FinFET is developed and verified to open up the possibility of the future SoC.

Anomalous diffusion of lightly implanted As into Si substrate during N2 annealing

We observe the anomalous diffusion of lightly implanted As into Si substrate during conventional furnace anneal in nitrogen ambient. The anomalous behavior shows two conspicuous features in the near‐surface region and in the tail region. In the near‐surface region reaching about 30–50 nm from the interface, a large number of As atoms moves toward the oxide/Si interface, and occasionally accumulates in a narrow region about 10–20 nm from the interface. Retarded diffusion is observed in the tail region. The diffusivity in the tail region increases with the increase of annealing time.

Advantage of Plasma Doping for Source/Drain Extension in Bulk Fin Field Effect Transistor

The impact of plasma doping (PD) on the formation of source/drain extension (SDE) is demonstrated for a p-type bulk fin field effect transistor (FinFET). The impurity distribution in a narrow fin (15 nm) was analyzed with atom probe tomography (APT) and secondary ion mass spectroscopy (SIMS). The lateral distribution of boron in the Si fin by the PD is similar to the case with conventional beam-line ion implantation (BL). However, the vertical distribution of boron by the PD is much steeper than that by the conventional BL. TCAD simulations show that the driving current of the FinFET fabricated by the PD is 34% higher than that of the FinFET fabricated by the BL under the same off-leakage current. Therefore, the PD is a key technology for fabricating the SDE of narrow bulk-FinFETs in the future.

Ultrashallow Junction Formation for Sub-100 nm Complementary Metal-Oxide-Semiconductor Field-Effect Transistor by Controlling Transient Enhanced Diffusion

The annealing process of implantation damage that induces transient enhanced diffusion during a subsequent thermal process such as low-pressure chemical vapor deposition (LPCVD) is optimized from the viewpoint of the process integration of an 80 nm physical gate length complementary metal-oxide-semiconductor field-effect transistor (CMOSFET) device. For nMOSFETs, a temperature as high as 960°C is necessary to prevent transient enhanced diffusion. In contrast, for pMOSFETs, higher temperature annealing promotes thermal diffusion instead of preventing enhanced diffusion. It is found that a separate annealing process sequence is required. In utilizing preamorphization implantation prior to boron implantation, however, higher temperature annealing is effective for forming an ultrashallow junction. Consequently, the annealing processes can be performed simultaneously.

Density-functional study on the dopant-segregation mechanism: Chemical potential dependence of dopant-defect complex at Si/SiO2 interface

Dopant segregation at Si/SiO2 interface has been a serious problem in silicon device technology. This paper reports a comprehensive density-functional study on the segregation mechanisms of boron, phosphorous, and arsenic at the Si/SiO2 interface. We found that three kinds of interfacial defects, namely, interstitial oxygen, oxygen vacancy, and silicon vacancy with two oxygen atoms, are stable in the possible chemical potential range. Thus, we consider these defects as trap sites for the dopants. For these defects, the dopant segregation energies, the electrical activities of the trapped dopants, and the kinetic energy barriers of the trapping/detrapping processes are calculated. As a result, trapping at the interstitial oxygen site is indicated to be the most plausible mechanism of the dopant segregation. The interstitial oxygen works as a major trap site since it has a high areal density at the Si/SiO2 interface due to the low formation energy.

Atomistic study of sulfur diffusion and S2 formation in silicon during low-temperature rapid thermal annealing

Theoretical analyses predict that large Schottky barrier reduction by sulfur doping at NiSi/Si junction is induced by S2 formation. The S2 formation may have occurred in silicidation process, even under low temperature rapid thermal annealing. We have demonstrated that implanted sulfur into silicon forms S2 configuration under low temperature rapid thermal annealing, based on first principles calculations and kinetic Monte Carlo (KMC) simulations.

Thermal-Annealing Effects on Dopant Redistribution in Nanoscale Si Fin

We investigated the diffusion of implanted boron and phosphorous in a narrow Si fin during rapid thermal annealing (RTA) at 1000 °C for 10 s. We found that the boron diffusion is described by the conventional diffusion model. We also found that the point defects (interstitial Si and vacancy) play an important role in determining the detailed distribution of boron in a narrow Si fin. On the other hand, the phosphorous diffusion shows anomalous behavior in the peak region of the Si fin, namely large dose loss from the Si region. We found experimentally that about 50% of implanted phosphorous atoms in the Si fin diffused out from the Si region by the annealing (1000 °C, 10 s). The simulation result shows that the experimental result of phosphorous diffusion is reproduced by taking into account the dose loss model through introduction of the interfacial trap layer. Because the phosphorous distribution is largely modified by the dose loss effect, it is considered that the large dose loss of phosphorous gives rise to large impacts on the device characteristics of fin field effect transistors (FinFETs).

Advantage of Plasma Doping for Source/Drain Extension in Bulk-FinFET

We demonstrate the impact of plasma doping (PD) on the formation of source/drain extension of a p-type bulk-FinFET. The impurity distribution in a narrow fin (20nm) was observed with atom prove tomography (APT) and secondary ion mass spectroscopy (SIMS). The lateral distribution of boron in the Si fin formed by the PD is found to be uniform, and it is similar to the case with conventional beam line (BL) implantation. However, the vertical distribution of boron by the PD is much steeper than that by the conventional BL implantation. Simulations show that the drive current of the FinFET fabricated by the PD is 34% higher than that by the BL implantation under the same off-leakage current. Therefore, the PD is a key technology to fabricate the SDE of narrow bulk FinFETs. Introduction FinFET is one of the promising candidates to extend the CMOS device scaling, since the double gate (DG) structure is suitable for reduction of short channel effect (SCE) which is most serious problem of decanano transistors. We have already reported the channel and punch through stopper (PTS) profiles in a narrow Si fin. We have also demonstrated the substantial improvement of device characteristics of bulk-FinFETs, such as the threshold voltage roll-off, the drain induced barrier lowering (DIBL) effect, and junction capacitance [1][2][3][4]. On the other hand, conformal doping around Si fin is necessary to reduce parasitic resistance. Therefore, ion implantation with large tilt angle has been applied to form the SED region of FinFETs [2], as well as the PD [5]. In particular, the advantage of the PD is obvious in the case of narrow interval of Si fins, since large tilt angle implantation is not adaptable in this case. It is, however, still not clarified whether the PD is superior to the conventional BL implantation for the SDE formation without tilt angle constraint. In this paper, we investigated detailed distribution of boron doped by PD and BL implantation in an isolated narrow Si fin, and found that the PD has been suitable to fabricate the SDE region of FinFETs. Sample Preparation Figure 2 shows the process flow of sample preparation to investigate the dopant distribution in this paper. Si fins were formed on p-type (100) Si wafers, and the spaces between Si fins were filled by SiO2. After partial removal of the SiO2 in the STI region, the PTS was formed by conventional BL implantation [2]. After SDE formation by PD or tilted BL implantation, the oxide in the STI regions was removed. Whole area was covered with amorphous Si (a-Si) and flattened by chemical mechanical polishing (CMP) according to the sample preparation technique in ref.[3]. The impurity distribution in the Si fin region was observed by secondary ion mass spectroscopy (SIMS) and atom probe tomography (APT). Figure 3 shows TEM image of Si fin sample with 20nm width. Importance of Re-crystallization of Si fin Defects in Si region due to high dose implantation should degrade the device characteristics, such as increase of both junction leakage current [6] and S/D extension resistance [7]. We observed the difference of crystallinity of Si fins doped by PD and BL implantation by TEM images, as shown in Figs. 4(a) and 5(a), respectively. The amorphous Si region due to helium bombardment during PD is observed. After spike annealing at 1045°C, the amorphous Si regions are perfectly recovered to single crystal Si, as seen in Fig. 4(b) and figure 5(b). It is, therefore, considered that the crystallinity of Si fin region doped by PD followed by thermal annealing is identical with that by BL implantation. Analysis of dopant distribution in narrow Bulk-FinFET Figure 6 shows an example of the APT analysis or impurity distribution. From this figure, we found that the APT successfully determines atomistic distribution in Si fin and cap region (a-Si). It is possible to identify the position of interface between Si fin and cap a-Si region, thanks to the oxygen distribution. Figure 7 shows lateral distribution in Si fin of boron doped by PD and BL implantation in three regions (A-C). These figures indicate that, in the narrow Si fin, both PD and BL implantation result in almost identical boron distribution at the SDE region. The validity of APT analysis is confirmed by comparison with the result of SIMS. Figure 8 shows boron depth distribution in the Si fin measured by the APT and SIMS for PD (a) and BL implantation (b), respectively. These figures show the excellent agreement with each other. Figure 9 shows both boron distributions for PD and BL implantation and arsenic distribution for conventional BL implantation by SIMS. Arsenic region acts as a PTS beneath the channel region of the bulk-FinFET, as well as boron region corresponds to the SDE. We see that the boron concentrations by PD and BL implantation are almost same in Si fin above the STI, while the boron distribution doped by PD is steeper than that by BL implantation in deeper region. Effect of SDE distribution on Device Characteristics We evaluate the impact of SDE boron distribution on device characteristics of p-type bulk-FinFET by 3D simulation. The simulation results for PD-SDE and BL-SDE are shown in Figs. 10(a) and (b). We found that the off-leakage current (Ioff) of BL-SDE is much larger than that of PD-SDE with same on current (Ion). It is attributed to the punch through leakage current beneath the channel region caused by the broader boron distribution of BL-SDE. In order to reduce the large Ioff, the impurity profile in PTS for BL-SDE should be optimized. Figure 11(b) shows the optimized arsenic PTS distribution for BL-SDE FinFET by simulation so as to be identical Ioff with that for the PD-SDE case (figure 11(a)). These figures show that the arsenic distribution for BL-SDE has higher concentration, wider and deeper PTS region than that for PD-SDE to suppress the leak current. Arsenic distribution of BL-SDE FinFET results in Ion degradation due to mobility lowering and narrowing of effective channel width. Simulation result shows that, in this case, PD-SDE FinFET has 34% higher Ion than that of BL-SDE FinFET. Conclusion In this paper, we investigated impurity distribution in a narrow Si fin region doped by the PD and tilted conventional BL implantation. The APT revealed that the lateral boron distribution doped by the PD is identical with that by BL implantation. However, vertical boron distribution of the PD is much steeper than that by the BL implantation. According to the difference of the vertical boron distribution, we found that the Ioff of p-type FinFET with PD-SDE is much smaller than that with BL-SDE. In addition, we tried to optimize the PTS distribution of BL-SDE FinFET by simulation so as to realize identical Ioff. We found that Ion of BL-FinFET is largely deteriorated, and PD-SDE FinFET has 34% higher on-current than BL-SDE FinFET. In conclusion, the PD technology is more suitable for the formation of SDE for narrow bulk-FinFET than conventional BL implantation. References [1] M. Kondo et al, SISPAD (2003) 179. [2] K. Okano et al, IEDM Tech. Dig. (2005) 739. [3] T. Izumida et al, SNW (2006) 127. [4] T. Kanemura et al, SISPAD (2006) 131. [5] D. Lenoble et al, Symp. on VLSI Tech (2006) 212. [6] K. Yako et al., IEDM Tech. Dig. (2008) 909. [7] C.-Y. Chang et al., IEDM Tech. Dig. (2009) -1022Extended Abstracts of the 2010 International Conference on Solid State Devices and Materials, Tokyo, 2010, pp1022-1023 C-7-3