Nobutoshi Aoki

Process integration technology and device characteristics of CMOS FinFET on bulk silicon substrate with sub-10 nm fin width and 20 nm gate length

The process integration schemes for CMOS FinFET fabricated on bulk Si substrate are discussed from the viewpoints of device size scalability and short channel effect control. The trimming technique by special oxidation was applied to reduce fin width down to sub-10 nm regime. A novel punch through stopper (PTS) formation process was introduced to the bottom of the channel region to scale the gate length down to 20 nm. The combination of both process technology enables us to fabricate the smallest FinFET on bulk Si substrate reported to date

High-Performance FinFET with Dopant-Segregated Schottky Source/Drain

High-performance CMOS-FinFET with dopant-segregated Schottky source/drain (DS-Schottky S/D) technology has been demonstrated. Thanks to the low parasitic resistance in DS-Schottky S/D, high drive current of 960 muA/mum was achieved for nFET with Lg = 15 nm and Wfin =15 nm at Vd= 1.0 V and Ioff= 100 nA/mum. Furthermore, the propagation delay time has been successfully improved down to less than 5 ps in the ring oscillator with DS-Schottky S/D CMOS-FinFET with 15 nm gate length

Fully-depleted FBC (floating body cell) with enlarged signal window and excellent logic process compatibility

Fully-depleted (FD) floating body cell on 55nm SOI featuring excellent logic process compatibility has been successfully developed. For the first time FD operation is reported through significant signal enlargement by negative substrate bias. Using standard salicide process and FD operation, high-density embedded memory on SOI is achievable.

A new substrate engineering for the formation of empty space in silicon (ESS) induced by silicon surface migration

A new technique to form empty spaces in silicon substrates is presented. The empty space with various shapes, such as plate as well as sphere and pipe, could be formed under the surface of the silicon substrate.

Embedded Bulk FinFET SRAM Cell Technology with Planar FET Peripheral Circuit for hp32 nm Node and Beyond

Integration schemes of bulk FinFET SRAM cell with bulk planar FET peripheral circuit are studied for the first time. Two types of SRAM cells with different beta-ratio were fabricated and investigated in the view of static noise margin (SNM). High SNM of 122 mV is obtained in the cell with 15 nm fin width, 90 nm channel height and 20 nm gate length at Vdd = 0.6 V. This is the smallest gate length FinFET SRAM reported to date. A higher beta ratio (beta> 2.0) in FinFET SRAM cell will be also achieved by tuning the effective channel width of each FinFETs without area penalty by taking advantage of bulk-Si substrate

Sidewall transfer process and selective gate sidewall spacer formation technology for sub-15nm finfet with elevated source/drain extension

We present the FinFET process integration technology including improved sidewall transfer (SWT) process applicable to both fins and gates. Using this process, the uniform electrical characteristics of the ultra-small FinFETs of 15nm gate length and 10 nm fin width have been demonstrated. A new process technique for the selective gate sidewall spacer formation (spacer formation only on the gate sidewall, no spacer on the fin sidewall) is also demonstrated for realizing low-resistance elevated source/drain (S/D) extension

SON (Silicon on Nothing) MOSFET using ESS (Empty Space in Silicon) technique for SoC applications

SON (Silicon on Nothing) MOSFET was successfully fabricated for the first time by using ESS (Empty Space in Silicon) technique as an alternative of SOI-MOSFET. Advantage of SON structure was experimentally demonstrated. SON structure using ESS technique is appropriate for System on a Chip (SoC) applications, such as embedded trench DRAMs and digital-analog mixed devices, due to the merit that SON structure can be fabricated partially on bulk substrate.

Impact of BOX scaling on 30 nm gate length FD SOI MOSFET

This paper presents the first demonstration of ultra-thin BOX FD SOI devices with nominal gate length of 30 nm. The characteristics of FD SOI MOSFETs are investigated in detail as T/sub BOX/ is varied from 5 nm to 145 nm. In addition, optimum design regions of T/sub BOX/ for achieving performance requirements are demonstrated.

A hp22 nm node low operating power (LOP) technology with sub-10 nm gate length planar bulk CMOS devices

High performance 10 nm gate length CMOSFETs for hp22 nm node LOP is demonstrated for the first time. Key process, such as elevated source/drain extension combined with flash lamp annealing, fully silicided metal gate, novel SiON, and optimization method under high V/sub dd/ condition which taking care of SRAM performance is described. Record high transconductance of 1706 mS/mm and over 400 GHz f/sub i/ is achieved for nMOSFET. Bulk planar MOSFET structure can extend down to hp22 nm node.

Issues and optimization of millisecond anneal process for 45 nm node and beyond

We have investigated millisecond anneal, such as laser spike annealing (LSA) and flash lamp annealing (FLA), which substitute for spike RTA as a dopant activation technology of source/drain extension for 45 nm node. Three key issues of gate leakage current, junction leakage current and pattern dependence were discussed from the integration and CMOSFETs performance viewpoint. We reported that LSA is the leading candidate for 45 nm node and beyond.