Takashi Izumida

Process integration technology and device characteristics of CMOS FinFET on bulk silicon substrate with sub-10 nm fin width and 20 nm gate length

The process integration schemes for CMOS FinFET fabricated on bulk Si substrate are discussed from the viewpoints of device size scalability and short channel effect control. The trimming technique by special oxidation was applied to reduce fin width down to sub-10 nm regime. A novel punch through stopper (PTS) formation process was introduced to the bottom of the channel region to scale the gate length down to 20 nm. The combination of both process technology enables us to fabricate the smallest FinFET on bulk Si substrate reported to date

High-Performance FinFET with Dopant-Segregated Schottky Source/Drain

High-performance CMOS-FinFET with dopant-segregated Schottky source/drain (DS-Schottky S/D) technology has been demonstrated. Thanks to the low parasitic resistance in DS-Schottky S/D, high drive current of 960 muA/mum was achieved for nFET with Lg = 15 nm and Wfin =15 nm at Vd= 1.0 V and Ioff= 100 nA/mum. Furthermore, the propagation delay time has been successfully improved down to less than 5 ps in the ring oscillator with DS-Schottky S/D CMOS-FinFET with 15 nm gate length

Embedded Bulk FinFET SRAM Cell Technology with Planar FET Peripheral Circuit for hp32 nm Node and Beyond

Integration schemes of bulk FinFET SRAM cell with bulk planar FET peripheral circuit are studied for the first time. Two types of SRAM cells with different beta-ratio were fabricated and investigated in the view of static noise margin (SNM). High SNM of 122 mV is obtained in the cell with 15 nm fin width, 90 nm channel height and 20 nm gate length at Vdd = 0.6 V. This is the smallest gate length FinFET SRAM reported to date. A higher beta ratio (beta> 2.0) in FinFET SRAM cell will be also achieved by tuning the effective channel width of each FinFETs without area penalty by taking advantage of bulk-Si substrate

Sidewall transfer process and selective gate sidewall spacer formation technology for sub-15nm finfet with elevated source/drain extension

We present the FinFET process integration technology including improved sidewall transfer (SWT) process applicable to both fins and gates. Using this process, the uniform electrical characteristics of the ultra-small FinFETs of 15nm gate length and 10 nm fin width have been demonstrated. A new process technique for the selective gate sidewall spacer formation (spacer formation only on the gate sidewall, no spacer on the fin sidewall) is also demonstrated for realizing low-resistance elevated source/drain (S/D) extension

Direct evaluation of DC characteristic variability in FinFET SRAM Cell for 32 nm node and beyond

Vt variability in FinFET SRAM is evaluated for the first time by direct measurement of the cell transistors down to 25 nm gate length. By taking the V, mismatch between Pull-Down transistors (PD) or between PD & Pass Gate transistor (PG), the dependence of V, variability on the cell transistor layout and channel impurity concentration was clearly observed. Read / Write margins in FinFET SRAM cell are also investigated by measuring both N-curves and their variability. The results suggest that FinFET is still a promising candidate for SRAM applications even in 32 nm node and beyond, if the appropriate cell design is applied.

Depletion-type Cell-Transistor of 23 nm Cell Size on Partial SOI Substrate for NAND Flash Memory

1. Abstract To reduce the short channel effect for memory cell transistors beyond 2Xnm cell size for NAND Flash memories, we propose a depletion-type cell transistor fabricated on a self-manufactured partial SOI substrate by conventional LSI process and solid phase epitaxy. The memory cell transistors with stack-gate show well program / erase properties and have the typical S-factor of 366mV/decay. Short channel effect is reduced substantially to available level for 2Xnm size NAND Flash memory.

Improvement of Drive Current in Bulk-FinFET using Full 3D Process/Device Simulations

We discussed the optimization of structure and doping profile of bulk-FinFETs by using 3D process and device simulations. The channel profile was determined so as to realize higher drive current as well as lower punch-through current. The analysis of stress field for bulk-FinFETs and SOI-FinFETs revealed that the channel stress induced by a stress liner (SL) in the bulk-FinFET is larger than that for the SOI-FinFET. In addition, we applied a raised source/drain (RSD) structure to the bulk-FinFETs and optimized doping profile in the RSD region. The combination of stress liner and RSD structure is found to be efficient for improving drive current of a bulk-FinFET

FinFET: the prospective multi-gate device for future SoC applications

This paper discusses the possibility of future large scale integration (LSI) of multi-gate device. FinFET is thought to he the most promising multi-gate device for LSI, because it easily realizes the self-aligned double-gate structure. At first, the feasibility of SRAM operation with FinFET in hp22 nm node is studied by simulation in terms of Vt fluctuation control. Next, it is demonstrated that FinFET on bulk Si substrate (bulk-FinFET) is a suitable candidate for cost-effective LSI manufacturing. The integration schemes of FinFET and planar FET on the same substrate are also developed for the fabrication of 128 Kbit SRAM ADM (array diagnostic monitor). Finally, successful SRAM cell operation is demonstrated with FinFET of Lg = 20 nm. Therefore, FinFET integrated circuit can provide a unique solution for future low-power SoC

FinFET Process and Integration Technology for High Performance LSI in 22 nm node and beyond

This paper discusses the key FinFET process and integration technologies to achieve high performance LSI. Firstly, side wall pattern transfer technique is introduced to realize an aggressively scaled down FinFET with 10 nm Fin width (Wfin) and 15 nm gate length (Lg). Next, dopant segregation (DS) Schottky technique is demonstrated to enhance the FinFET performance. Drive current of 960 muA/mum for DS Schottky nFinFET with Lg = 15 nm at Ioff = 100 nA/mum and Vd= 1.0 V is achieved. And then, FinFET SRAM is fabricated and studied in the view of static noise margin (SNM). SNM of 122 mV is obtained in the cell with Wfin = 15 nm and Lg = 20 nm at Vd = 0.6 V. Also, fin height tuning technique is proposed so that SRAM operation can be optimized without area penalty. Finally, integration scheme of planar FET and FinFET is developed and verified to open up the possibility of the future SoC.

Advantage of Plasma Doping for Source/Drain Extension in Bulk Fin Field Effect Transistor

The impact of plasma doping (PD) on the formation of source/drain extension (SDE) is demonstrated for a p-type bulk fin field effect transistor (FinFET). The impurity distribution in a narrow fin (15 nm) was analyzed with atom probe tomography (APT) and secondary ion mass spectroscopy (SIMS). The lateral distribution of boron in the Si fin by the PD is similar to the case with conventional beam-line ion implantation (BL). However, the vertical distribution of boron by the PD is much steeper than that by the conventional BL. TCAD simulations show that the driving current of the FinFET fabricated by the PD is 34% higher than that of the FinFET fabricated by the BL under the same off-leakage current. Therefore, the PD is a key technology for fabricating the SDE of narrow bulk-FinFETs in the future.