Sanchita Mal-Sarkar

Hardware trojan attacks in FPGA devices: threat analysis and effective counter measures

Reconfigurable hardware including Field programmable gate arrays (FPGAs) are being used in a wide range of embedded applications including signal processing, multimedia, and security. FPGA device production is often outsourced to off-shore facilities for economic reasons. This opens up the opportunities for insertion of malicious design alterations in the foundry, referred to as hardware Trojan attacks, to cause logical and physical malfunction. The vulnerability of these devices to hardware attacks raises security concerns regarding hardware and design assurance. In this paper, we analyze hardware Trojan attacks in FPGA considering diverse activation and payload characteristics and derive a taxonomy of Trojan attacks in FPGA. To our knowledge, this is the first effort to analyze Trojan threats in FPGA hardware. Next, we propose a novel redundancy-based protection approach based on Trojan tolerance that modifies the application mapping process to provide high-level of protection against Trojans of varying forms and sizes. We show that the proposed approach incurs significantly higher security at lower overhead than conventional fault-tolerance schemes by exploiting the nature of Trojans and reconfiguration of FPGA resources.

Uncertainty-aware Wireless Sensor Networks

The characterisation of uncertainty and the management of Quality of Service are important issues in mobile communications. In a Wireless Sensor Network, there is a high probability of redundancy, correlation and noise in the sensor features since data is often collected from a large array of densely deployed neighbouring sensors. This article proposes a soft computing approach to manage uncertainty by reasoning over inconsistent, incomplete, and fragmentary information using classical rough set and dominance-based rough set theories. A methodological and computational basis is provided and is illustrated in a real world sensor network application of aquatic biodiversity mapping under uncertainty.

Golden-Free Hardware Trojan Detection with High Sensitivity Under Process Noise

Malicious modification of integrated circuits in untrusted design house or foundry has emerged as a major security threat. Such modifications, popularly referred to as Hardware Trojans, are difficult to detect during manufacturing test. Sequential hardware Trojans, usually triggered by a sequence of rare events, represent a common and deadly form of Trojans that can be extremely hard to detect using logic testing approaches. Side-channel analysis has emerged as an effective approach for detection of hardware Trojans. However, existing side-channel approaches suffer from increasing process variations, which largely reduce the detection sensitivity and sets a lower limit of the sizes of Trojans detectable. In this paper, we present TeSR, a Temporal Self-Referencing approach that compares the current signature of a chip at two different time windows to isolate the Trojan effect. Since it uses a chip as a reference to itself, the method completely eliminates the effect of process noise and other design marginalities (e.g. capacitive coupling), thus providing high detection sensitivity for Trojans of varying size. Furthermore, unlike most of the existing approaches, TeSR does not require a golden reference chip instance, which may impose a major limitation. Associated test generation, test application, and signature comparison approaches aimed at maximizing Trojan detection sensitivity are also presented. Simulation results for three complex sequential designs and three representative sequential Trojan circuits demonstrate the effectiveness of the approach under large inter- and intra-die process variations. The approach is also validated with current measurement results from several Xilinx Virtex-II FPGA chips.

Application of wireless sensor networks in forest fire detection under uncertainty

This paper proposes a soft computing approach to manage uncertainty and rule discovery by reasoning over inconsistent, incomplete and fragmentary information using dominance-based rough set theories. A methodological and computational basis is illustrated in a sensor network application scenario of a forest fire detection system.

Design and Validation for FPGA Trust under Hardware Trojan Attacks

Field programmable gate arrays (FPGAs) are being increasingly used in a wide range of critical applications, including industrial, automotive, medical, and military systems. Since FPGA vendors are typically fabless, it is more economical to outsource device production to off-shore facilities. This introduces many opportunities for the insertion of malicious alterations of FPGA devices in the foundry, referred to as hardware Trojan attacks, that can cause logical and physical malfunctions during field operation. The vulnerability of these devices to hardware attacks raises serious security concerns regarding hardware and design assurance. In this paper, we present a taxonomy of FPGA-specific hardware Trojan attacks based on activation and payload characteristics along with Trojan models that can be inserted by an attacker. We also present an efficient Trojan detection method for FPGA based on a combined approach of logic-testing and side-channel analysis. Finally, we propose a novel design approach, referred to as Adapted Triple Modular Redundancy (ATMR), to reliably protect against Trojan circuits of varying forms in FPGA devices. We compare ATMR with the conventional TMR approach. The results demonstrate the advantages of ATMR over TMR with respect to power overhead, while maintaining the same or higher level of security and performances as TMR. Further improvement in overhead associated with ATMR is achieved by exploiting reconfiguration and time-sharing of resources.

Secure and Trusted SoC: Challenges and Emerging Solutions

Over the ages, hardware components, platforms and supply chains have been considered secure and trustworthy. However, recent discoveries and reports on security vulnerabilities and attacks in microchips and circuits violate this hardware root of trust. System-on-Chip (SoC) design based on reusable hardware intellectual property (IP) is now a pervasive design practice in the industry due to the dramatic reduction in design/verification cost and time. This growing reliance on reusable pre-verified hardware IPs and a wide array of design automation tools during SoC design, often acquired from untrusted 3rd party vendors, coupled with fabrication in untrusted offshore foundries severely affects the security and trustworthiness of SoCs used in diverse applications. This paper presents an overview of the various security challenges in the SoC design cycle and possible solutions for protection.

Spatio-temporal template discovery using rough set theory

Real-time stream data is characterized by spatial and temporal variability and is subject to unbounded or constantly evolving entities. The challenge is how to aggregate these unbounded data streams at different spaces and times to provide effective decisions making in real-time. This paper proposes a rough set-based sliding window framework for stream data aggregation. Based on current data streams, it identifies interesting spatio-temporal patterns, and generates rough set If … Then decision rules. Proposed formalism has been tested on sea surface temperature data from NOAAs TAO/TRITON project. Such a pattern-based data aggregation scheme has the potential to significantly reduce data communications in decision making.