Sandeep R. Bahl

Extraction of Dynamic On-Resistance in GaN Transistors: Under Soft- and Hard-Switching Conditions

In this paper we present a new measurement technique for extracting dynamic on-resistance (Rdson) of GaN transistors. Dynamic Rdson of commercial GaN transistors in soft-switching and hard-switching conditions have been measured. By comparing the dynamic Rdson in both switching schemes, it is found that the off-state drain voltage stress is the main cause for the increase of dynamic Rdson, while the switching losses in the hard-switching transient could cause additional trapping and degradation, possibly due to channel hot electrons/phonons.

Physics, Technology, and Modeling of Complementary Asymmetric MOSFETs

The physics, technology, and modeling of complementary asymmetric MOSFETs are reviewed and illustrated with statistically representative silicon data from a recent manufacturing implementation, in which the transistors for the secondary power supply voltage are offered in asymmetric and symmetric constructions. The in-depth analysis of the device physics of asymmetric transistors provides new insights into their physical operation and into the operation of transistors using halo implants in general. The variability, matching, and noise implications of using halo implants are also analyzed, concluding that both asymmetric and symmetric devices need to be offered for uncompromised circuit design. The challenges associated with the compact modeling the asymmetric transistors are also reviewed and illustrated. The preferred manufacturing implementation uses retrograde wells with no dopant fillers at the surface, while avoiding the drain-to-source punch-through by source-side-only halo implants. In addition to the known switching speed and maximum voltage gain advantages of the asymmetric transistors, this particular device architecture offers superior hot-carrier reliability and transistor design flexibility. The availability of retrograde wells enables construction of high-reliability complementary extended-drain MOSFETs for a third higher power supply voltage.

Enhanced PMOS NBTI degradation due to halo implant channeling

NBTI is a serious reliability concern in state of the art PMOSFET devices. The implementation of nitrided gate oxides to prevent boron penetration has aggravated the NBTI issue. Because of relaxation effects careful stress and measurement techniques (ldquoOn-the-Flyrdquo) must be used for reliable estimation of device lifetime. This abstract describes a unique enhanced NBTI degradation phenomenon in which NBTI induced VT degradation was determine to be directly proportional to the initial VT of the device. Electrical results from special test structures identified halo implant channeling as causing the enhanced NBTI induced degradation behavior.