Sang-hyup Kwak

A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction

This paper describes a 1 Gbit GDDR5 SDRAM with enhanced bank access flexibility for efficient data transfer in 7 Gb/s per pin IO bandwidth. The enhanced flexibility is achieved by elimination of bank group restriction and reduction of bank to bank active time to 2.5 ns. The effectiveness of these key features is verified by system model simulation including memory and its controller. To realize the enhanced bank access flexibility, this DRAM employs the following techniques: skewed control logic, PVT variation compensated IO sense amplifier with auto calibration by replica impedance monitor, FIFO based BLSA enable signal generator, low latency VPP generator and active jitter canceller. This GDDR5 SDRAM was fabricated in 50 nm standard DRAM process in 61.6 die area and operates with 1.5 V power supply.

A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW

Most DRAM interfaces such as GDDR5 and DDR3 use parallel single-ended signaling due to pin-count restriction and backward compatibility. Notwithstanding poor signal and power integrity issues, GDDR5 speed reached beyond 5Gb/s in recent years by utilizing data bus inversion, error-detection coding, data training and channel equalization [1–3]. However, channel crosstalk is becoming a major barrier to further speed improvement. A common solution for channel crosstalk reduction at the system level is to use a shielding line or wide spacing between signal lines, but increasing the number of layers in a chip package and PCB increase system cost. To remove the shielding lines and increase speed, this paper presents a channel crosstalk equalizer with programmable signal ordering capability for the DRAM transmitter. In addition, this paper addresses tri-mode clocking to reduce the system jitter for better timing margin: PLL off, LC-PLL and injection-locked oscillator.

A 40nm 7Gb/s/pin single-ended transceiver with jitter and ISI reduction techniques for high-speed DRAM interface

A 7Gb/s single ended transceiver with low jitter and ISI is implemented in 40nm DRAM process. DRAM optimized LC PLL achieves inductor Q of 3.86 and results in random jitter of 670fs rms. A clock tree regulator with closed loop replica path reduces low as well as high frequency noise. RX 2-tap hybrid DFE combining sampling and integration methods reduces power and area by 37% and 24%, compared to the integrating DFE. Moreover, on-chip de-emphasis circuit in TX multiplexer reduces ISI of both on and off chip.