Young-Kwan Cha

Highly-scalable threshold switching select device based on chaclogenide glasses for 3D nanoscaled memory arrays

We present here on a switch device made of a nitridized-chalcogenide glass for application in nanoscale array circuits. Previously, AsTeGeSi-based switches have had key issues with performance degradation over time. This is usually due to changes in the Te concentration in the device active region [1-3]. However, our AsTeGeSiN switches were able to overcome this limitation as well as scale down to 30 nm with an on current of 100 μA (J > 1.1×107A/cm2). Their cycling performance was shown to be greater than 108. Also, we demonstrate a memory cell using a TaOx resistance memory with the AsTeGeSiN select device.

Atomic-layer deposited IrO2 nanodots for charge-trap flash-memory devices

Charge-trap flash- (CTF) memory structures have been fabricated by employing IrO2 nanodots (NDs) grown by atomic-layer deposition. A band of isolated IrO2NDs of about 3 nm lying almost parallel to Si/SiO2 interface is confirmed by transmission electron microscopy and x-ray photoelectron spectroscopy. The memory device with IrO2NDs shows much larger capacitance–voltage (C–V) hysteresis and memory window compared with the control sample without IrO2NDs. After annealing at 800 °C for 20 min, the ND device shows almost no change in the width of C–V hysteresis and the ND distribution. These results indicate that the IrO2NDs embedded in SiO2 can be utilized as thermally stable, discrete charge traps, promising for metal oxide-ND-based CTF memory devices.

Multibit memories using a structure of SiO2/partially oxidized amorphous Si∕HfO2

Memory capacitors with a structure of SiO2/partially oxidized amorphous Si (a-Si)/HfO2 have been prepared by sequential processes: atomic layer deposition (ALD) of 6nm a-Si on 3.5nm SiO2, thermal oxidation at 900°C, and another ALD of 12nm HfO2. The memory devices offer hybrid type of charge memory: the interface states of partially oxidized a-Si∕SiO2 tend to act as hole traps, resulting in a negative shift of flatband voltage in capacitance-voltage (C-V) curve, and the partially oxidized a-Si∕HfO2 interface has dominantly electron-trap centers, leading to a positive voltage shift. By this hybrid effect, the memory window in C-V curve is observed to be enlarged enough to realize four-level (2bit) memories, which is demonstrated through measurements of program/erase speeds and charge-loss rates.

Effect of hydrogenation on the memory properties of Si nanocrystals obtained by inductively coupled plasma chemical vapor deposition

Effect of hydrogenation on memory properties has been studied for metal-oxide-semiconductor (MOS) structures with Si nanocrystals fabricated using inductively coupled plasma chemical vapor deposition and subsequent annealing. Hydrogenation induces a drastic increase of a dip in the quasistatic capacitance-voltage (C-V) curve of the MOS capacitor, caused by the reduction of the interface states due to hydrogen passivation. This is consistent with high-frequency C-V measurements showing more well-defined curves with less distortion in hydrogenated samples. After hydrogenation, the MOS device shows a significantly larger decrease of flatband voltage shift in electron charging than in hole charging, indicating more effective passivation of the defect states related to the electron charging. A longer retention time is found for electron charging after hydrogenation, but almost no change of charge loss rate for hole charging. These results suggest that an asymmetry exists in the effect of hydrogenation between ...

Novel transition layer engineered Si nanocrystal flash memory with MHSOS structure featuring large V/sub th/ window and fast P/E speed

In this work, we propose a MHSOS (metal gate/high-k/SRO(silicon-rich oxide)/SiO2/Si) structure showing large memory window (> 4V) with fast P/E speed (plusmn18 V, 200 mus). The erase speed is featuring faster than that of Si3 N4 and has a retention time of 10 years for 10 % charge loss. These excellent properties were obtained through the modification of the transition layer between Si-NC and SiO2 matrix in an SRO medium, as well as tunneling/blocking dielectric material optimization

A New Operating Scheme by Switching the Polarity of Program/Erase Bias for Partially Oxidized Amorphous-Si-Based Charge-Trap Memory

In this brief, the authors propose a new program/erase (P/E) scheme for NAND-type partially oxidized amorphous-Si (a-Si)-based charge-trap memory in which the P/E voltages are interchanged into negative/positive ones, respectively. In the a-Si memory, the erasing speed was found to be faster than the programming speed, and therefore, the new scheme has been chosen to keep the program speed faster than the erase speed for the NAND operation. The P/E speeds in the new scheme increase at least ten times as those in the conventional P/E scheme. It is also shown that four-level memory states can be achieved via Fowler-Nordheim tunneling by applying programming voltage of -16, -18, and -20 V for each level during only 40 mus together with erasing voltage pulse (+20 V, 1 ms). These results indicate that the new P/E scheme is more effective than the conventional scheme for operating the partially oxidized a-Si-based memories