Wooseung Choo

A multistandard multiband mobile TV RF SoC in 65nm CMOS

The mobile TV applications such as DVH-H/T, T-DMB/DAB, ISDB-T are recently emerging all over the world. To support various applications, the multistandard and multiband mobile TV RF tuner is developed as a cost-effective and size-effective solution [1]. The demand for smaller form factor and power consumption reduction of RF and Channel is very high, and SoC technology is being adopted to meet the customers requirements. As shown in Fig. 25.7.1, an SoC that implements all of the standards and frequency bands of a mobile TV in a 65nm CMOS is presented in this paper. This RF SoC consists of three RF front ends, a dual-mode analog baseband filter supporting lowpass filtering and complex bandpass filtering, a digitally controlled programmable-gain amplifier (PGA), wideband VCO/PLL, DCXO, data converters, demodulator, forward error correction (FEC), hardwired multiprotocl encapsulation forward error correction (MPE-FEC), ARM CPU and SRAM. This mobile TV RF SoC reduces board area and complexity while cutting system design time.

Design and Analysis of a Cascode Bipolar Low-Noise Amplifier With Capacitive Shunt Feedback Under Power-Constraint

A cascode bipolar low-noise amplifier (LNA) with capacitive shunt feedback has been developed to present a solution for simultaneous noise and power match when the real part of the optimum source impedance is not 50 Ω in order to keep high current density under power constraint. The proposed LNA also has the capability for the simultaneous improvement of noise figure (NF) and linearity. In addition, we analyzed and verified that the second-order interaction, which affects the third-order nonlinearity, becomes less sensitive to the low-frequency input termination at higher bias currents. The possibility of removing the low-frequency LC trap is investigated based on this analysis. We also show that LNAs with smaller base and/or smaller emitter resistances require lower source impedance at low frequencies to improve linearity by the same amount. Finally, prudent layouts for improving the performance of the LNA are considered. Eleven design examples of the proposed LNA, which individually operate at 880, 1575, or 1960 MHz, are fabricated in a low-cost 0.35- μm SiGe BiCMOS process to verify the design and analysis experimentally. The fabricated LNAs have excellent performances, especially in NF. For example, the 880-MHz LNA has an NF of 0.9 dB, a power gain of 16 dB, and an IIP3 of +14 dBm with current consumption of 11 mA from a 2.8-V power supply.

A multi-standard multi-band tuner for mobile TV SoC with GSM Interoperability

A multi-standard multi-band tuner for mobile TV SoC satisfying the GSM850 & GSM900 Interoperability (IOP) is presented. The single-chip SoC satisfies all requirements of DVB-H/T, ISDB-T, and DAB application with margin. Moreover, this SoC meets not only the GSM900 IOP which is described in MBRAI 2.0, but also GSM850 IOP, in DVB-T/H mode. To suppress GSM transmitter signal in UHF band, LC-tuned load and tunable input matching scheme are adopted in UHF LNA. The SoC consists of three RF LNAs covering the 174 to 248MHz (VHF), 470 to 862MHz (UHF), and 1450 to 1490MHz (L-BAND) bands, dual mode analog baseband filter supporting low pass filtering for direct conversion in DVB-H/T mode and complex band pass filtering for low-IF conversion in ISDB-T 1-segmentation and DAB. The measured sensitivity at UHF for the QPSK 1/2 DVB-T mode is under −95.5dBm with GSM rejection filter.

Dual-Path

This letter describes a dual-path LC voltage controlled oscillator (VCO) design that reduces both coarse-tuning and fine-tuning sensitivities. By using a combination of discrete and continuous tuning methods for the coarse-tuning control, a very high gain ratio between the coarse-tuning path and the fine-tuning path can be avoided, significantly alleviating noise and coupling problems due to high coarse-tuning gain. A 3.03-3.67 GHz dual-path VCO in 65 nm CMOS exhibits -120.7 dBc/Hz at a 400 kHz offset from a 1.73 GHz carrier, showing better performance than the conventional single-path VCO that is implemented for comparison.

LC

A highly integrated direct conversion receiver for cellular code division multiple access (CDMA) and GPS applications is successfully developed using a 0.5-/spl mu/m SiGe BiCMOS technology. The receiver consists of two low-noise amplifiers (LNAs), a dual-band mixer, two voltage-controlled oscillators (VCOs), a local-oscillator signal generation block, and channel filters. The CDMA LNA achieves a noise figure of 1.3 dB, an input-referred third-order intercept point (IIP3) of 10.9 dBm, and a gain of 15.3 dB with a current consumption of 9.8 mA in the high-gain mode. The mixer for the CDMA mode achieves an uncalibrated input-referred second-order intercept point of 53.7 dBm, an IIP3 of 6.4 dBm, a noise figure of 7.2 dB and a voltage gain of 37.2 dB. The phase noise of the CDMA VCO is approximately -133 dBc/Hz at a 900-kHz offset from a 1.762-GHz operating frequency. It exceeds all the CDMA requirements when tested on a handset.

VCO Design With Partitioned Coarse-Tuning Control in 65 nm CMOS

A triband 65nm CMOS tuner is designed and implemented for first ATSC mobile DTV SoC. It supports VHF-I, VHF-III, and UHF bands. The tuner achieves a 2.5/3.0/4.0dB NF at VHF-I, VHF-III and UHF band respectively, while consuming less than 100mW. By using narrowband LNA architecture with input and load tuning ability, it can meet linearity requirement for ATSC mobile with small power consumption. It also automatically calibrates baseband low-pass filter cut-off frequency and LNA LC load resonant frequency.

A dual-b and RF front-end of direct conversion receiver for wireless CDMA cellular phones with GPS capability

In this paper, a cascode bipolar low noise amplifier (LNA) employing a shunt feedback capacitor is presented, for which the linearity and the noise figure (NF) can be optimized by reducing the transistor size and degeneration inductance. We also show that the second-order interaction, which affects the third-order nonlinearity, becomes insensitive to low-frequency input termination as the DC current increases. Finally, the method of removing the low-frequency trap is presented. The fabricated LNA in 0.35-mum SiGe BiCMOS process showed NF of 0.9 dB with 16-dB power gain and IIP3 of +11 dBm with current consumption of 10 mA from 2.8-V power supply at 900 MHz. The demonstrated LNA satisfies stringent sensitivity and linearity requirement of code-division multiple-access (CDMA) applications quite well.

A triband 65nm CMOS tuner for ATSC mobile DTV SoC

An IP2 calibration technique is developed using the common mode feedback circuitry in a direct-conversion receiver for wireless CDMA/PCS/GPS/FM applications. The IP2 calibrator is capable of providing a different CMFB gain to tune its common mode output impedance for each of the positive and negative mixer outputs. The method performs a 20-dB improvement in IIP2. The CDMA mixer achieves an uncalibrated IIP2 of 44 dBm, an IIP3 of 4 dBm, a noise figure of 6.5 dB and a voltage gain of 42.2 dB. The receiver RFIC is implemented in a 0.5 /spl mu/m SiGe BiCMOS process, and it operates from a 2.7 to 3.1 V single power supply. It exceeds all CDMA requirements when tested individually or on a handset.

Design and analysis of a high-performance cascode bipolar low noise amplifier with shunt feedback capacitor

This paper presents a low-noise ΔΣ fractional-N PLL utilizing a mixed-mode triple-input LC VCO. An analog dual-path VCO control relaxes the nonlinearity problem of the ΔΣ fractional-N PLL, while a combination of discrete and continuous tuning methods for coarse-tuning control significantly alleviates the noise coupling problem caused by the high gain coarse-tuning path. A 3.6GHz ΔΣ fractional-N PLL implemented in 65nm CMOS exhibits nearly −100dBc/Hz in-band noise contribution and −53dBc in-band fractional spur performances from a 1.8GHz carrier.

IP2 calibrator using common mode feedback circuitry

An Ultra-wideband (UWB) transmitter is proposed that can correct phase errors in quadrature local (LO) signals automatically without help of baseband processor (BBP), operating from 3 to 9 GHz in 65 nm CMOS. The measured tuning range for sideband rejection is 32.7 dB at 7.7 GHz and 13.6 dB at 8.7 GHz. The measured EVM is lower than −20 dB for all supporting bands and TFCs (Time frequency codes) that are prescribed by WiMedia alliance. The power consumption of the transmitter including LO path and PLLs is 210 mW from a 1.2 V supply.