Sanjay Prajapati

Magnetic Domain Wall Race Track Memory

During the past four decades, semiconductor industry has witnessed a race between the development of processing devices/systems and memory technologies following the Moore’s law. With the end of Moore’s era on the silicon roadmap, the processing technologies are apparent frontrunner than the memory counterparts in terms of accessing speed and integration volumes.

Spin Orbit Torque MRAM

The STT (spin-transfer torque) has emerged as a promising memory technology to provide energy efficient, non-volatile, high density memories with low power dissipation and unlimited endurance. In addition, it offers CMOS compatible architectures with high-speed read and write operations. During the initial phase of the development, researchers envisaged the greater potential of the STT based magnetic random access memory (MRAM) to become an alternate solution of the contemporary memory technologies.

Next Generation 3-D Spin Transfer Torque Magneto-resistive Random Access Memories

Spin transfer torque magneto-resistive random access memories (STT MRAMs) are non-volatile memories that potentially demonstrate high speed and integration density. These exclusive features of STT MRAMs are rapidly gaining attention of memory designers. They are strong contenders for futuristic embedded memory applications. However, further reduction in write power dissipation and cell size is essential to employ STT MRAMs for embedded applications.

Multilevel Cell MRAMs

Over the past three decades, several memory technologies have made their place in the market with varying degrees of commercial success, such as erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), static random-access memory (SRAM), dynamic RAM (DRAM), and NAND/NOR flash memories, with varying degrees of commercial success. In general, computer systems employ a memory hierarchy using different types of memories used at different levels. At the highest level, on-chip high speed cache static-RAMs (SRAMs) are used; whereas, at the next higher level, high density, low power off-chip DRAMs are used as a main memory.

Emerging Memory Technologies

In conventional memory hierarchy, memories near and away from the processor provide short and long latencies (see Fig. 1.1), respectively.

Novel compact model for multi-level spin torque magnetic tunnel junctions

Spin-transfer torque (STT) and spin-orbit torque (SOT) based magnetic tunnel junction (MTJ) devices are emerging as strong contenders for the next generation memories. Conventional STT magneto-resistive random access memory (MRAM) offers lower power, non-volatility and CMOS process compatibility. However, higher current requirement during the write operation leads to tunnel barrier reliability issues and larger access devices. SOT-MRAM eliminates the reliability issues with strong spin polarized current (100%) and separate read/write current paths; however, the additional two access transistors in SOT-MRAM results into increased cell area. Multilevel cell (MLC) structure paves a way to circumvent the problems related to the conventional STT/SOT based MTJ devices and provides enhanced integration density at reduced cost per bit. Conventional STT/SOT-MRAM requires a unit cell area of ~10-60 F2 and reported simulations have been based on available single-level MTJ compact models. However, till date no compact model exists that can capture the device physics of MLC-MTJ accurately. Hence, a novel compact model is proposed in this paper to capture the accurate device physics and behaviour of the MLC-MTJs. It is designed for MLCs with different MTJ configurations demonstrated so far, such as series and parallel free layer based MLC-MTJs. The proposed model is coded in Verilog-A, which is compatible with SPICE for circuit level simulations. The model is in close agreement with the experimental results exhibiting an average error of less than 15%.