Shivam Verma

Novel 4 F 2 Buried-Source-Line STT MRAM Cell With Vertical GAA Transistor as Select Device

Spin transfer torque (STT) magnetic random access memories (MRAMs) have recently emerged as one of the strongest contenders for universal memory technology. They have entire range of features, i.e., high speed, nonvolatility, high density, and low power, which make them cynosure to every memory designers notion. Researchers are working ardently to use STT MRAMs under continuously increasing scaling challenges. To accommodate a larger amount of embedded memory, the cell size must be reduced. Therefore, the designs target to attain an optimistic figure of 4F2 (F being the feature size) array density, which is the maximum achievable two-dimensional (2-D) density. With this objective in mind, a novel 4F2 buried-source-line (SL) STT MRAM cell structure with a vertical gate all around (GAA) cylindrical buried source NMOS transistor is proposed. The magnetic tunnel junction (MTJ) multilayer structure is stacked above the select device with both occupying the same 2-D area. The diameters of perpendicular MTJ and vertical silicon nanowire are equal (i.e., F). Device simulations have been carried out on TCAD for buried source vertical GAA device structure. Furthermore, these TCAD results are used to calibrate the BSIM CG model for cylindrical GAA transistors. The proposed STT MRAM cell is then analyzed using calibrated Verilog-A models for perpendicular anisotropy MTJ and vertical GAA NMOS transistor (BSIM CG). The performance analysis in terms of read stability, write margins, and power dissipation for the proposed cell is also presented.

Modeling of In-Plane Magnetic Tunnel Junction for Mixed Mode Simulations

The incredible potentials of spin transfer torque (STT) magnetic random access memories (MRAMs) give them an edge over other memory technologies. Most of the projections show them as universal memory in the future; however, their evolution is still in a rudimentary stage. Attaining a high density in STT MRAMs is imperative to keep pace with the scaling scenario in field effect transistors (FETs) and hence competitive with future processors. A vertical or a two terminal select device can be a possible solution to achieve the high-density problem. A suitable platform is required for simulating a hybrid magnetic tunnel junction (MTJ)/FET circuit before an actual fabrication is done. However, most simulation tools do not have the capability to model hybrid MTJ/FET devices. Also, the SPICE compatible models for such devices and other novel structures like vertical FET are not available. This paper addresses the above-mentioned concerns and proposes a model for MTJ (coded in C++) and a simulation platform for hybrid MTJ/FET device-circuit co-design with physics-based models. The proposed model is validated using mixed mode simulations.

Bus encoder design for crosstalk and power reduction in RLC modelled VLSI interconnects

Purpose – This paper aims to reduce the worst-case crosstalk effects for resistance, inductance and capacitance (RLC) interconnects using the bus encoding technique. In current nanoscale technology, power dissipation, propagation delay and crosstalk performance of interconnects determine the overall performance of a chip. Signal integrity issues due to crosstalk in the form of voltage glitches, overshoots, undershoots, undesirable noise, propagation speed ups and downs, etc. are some of the major deterrents for high-performance RLC modelled (VLSI) interconnects. This research paper primarily proposes two novel encoding methods (I and II) for RLC modelled interconnects to reduce the effect of crosstalk, simultaneous switching noise (SSN) and power consumption. Design/methodology/approach – The proposed methods are based on the bus encoding method that is effective and well-suited for the reduction of the crosstalk noise. This method encodes or transforms incoming data in a manner that encoded data contain ...

Magnetic Domain Wall Race Track Memory

During the past four decades, semiconductor industry has witnessed a race between the development of processing devices/systems and memory technologies following the Moore’s law. With the end of Moore’s era on the silicon roadmap, the processing technologies are apparent frontrunner than the memory counterparts in terms of accessing speed and integration volumes.

Low-Power High-Density STT MRAMs on a 3-D Vertical Silicon Nanowire Platform

In recent years, researchers have focused toward reduction in power dissipation and cell size to employ spin-transfer torque (STT) magnetic random-access memories (MRAMs) for embedded applications. Hence, the magnetic tunnel junctions (MTJs) with an optimized structure and magnetic properties are being explored to reduce the switching current. However, the switching current reduction in the MTJs generally lowers the data-retention capability. Hence, a different approach to reduce power dissipation using a novel select device should be considered. This paper, therefore, explores the STT MRAM with vertical silicon nanowire gate all around (GAA) high-k select device for superior performance. The MTJ is stacked above the vertical GAA device, so that both occupy the same footprint area to achieve high array density. Furthermore, enhancement of current drive using high-k gate dielectric and its impact on the STT MRAMs are analyzed at different feature sizes. The proposed STT MRAM cell with high-k dielectric (HfO2) lowers the power dissipation by 8%-25% and increases the write margins (WMs) up to 38%, with negligible increment in delay in comparison with the GAA device using low-k dielectric (SiO2). Moreover, asymmetricity is introduced in device configuration to achieve power savings of 25%-30% at high VDD. The proposed asymmetric high-k cell offers a substantially larger tradeoff window between high WMs and low power dissipation.

Spin Orbit Torque MRAM

The STT (spin-transfer torque) has emerged as a promising memory technology to provide energy efficient, non-volatile, high density memories with low power dissipation and unlimited endurance. In addition, it offers CMOS compatible architectures with high-speed read and write operations. During the initial phase of the development, researchers envisaged the greater potential of the STT based magnetic random access memory (MRAM) to become an alternate solution of the contemporary memory technologies.

Next Generation 3-D Spin Transfer Torque Magneto-resistive Random Access Memories

Spin transfer torque magneto-resistive random access memories (STT MRAMs) are non-volatile memories that potentially demonstrate high speed and integration density. These exclusive features of STT MRAMs are rapidly gaining attention of memory designers. They are strong contenders for futuristic embedded memory applications. However, further reduction in write power dissipation and cell size is essential to employ STT MRAMs for embedded applications.

Multilevel Cell MRAMs

Over the past three decades, several memory technologies have made their place in the market with varying degrees of commercial success, such as erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), static random-access memory (SRAM), dynamic RAM (DRAM), and NAND/NOR flash memories, with varying degrees of commercial success. In general, computer systems employ a memory hierarchy using different types of memories used at different levels. At the highest level, on-chip high speed cache static-RAMs (SRAMs) are used; whereas, at the next higher level, high density, low power off-chip DRAMs are used as a main memory.

Emerging Memory Technologies

In conventional memory hierarchy, memories near and away from the processor provide short and long latencies (see Fig. 1.1), respectively.

Novel compact model for multi-level spin torque magnetic tunnel junctions

Spin-transfer torque (STT) and spin-orbit torque (SOT) based magnetic tunnel junction (MTJ) devices are emerging as strong contenders for the next generation memories. Conventional STT magneto-resistive random access memory (MRAM) offers lower power, non-volatility and CMOS process compatibility. However, higher current requirement during the write operation leads to tunnel barrier reliability issues and larger access devices. SOT-MRAM eliminates the reliability issues with strong spin polarized current (100%) and separate read/write current paths; however, the additional two access transistors in SOT-MRAM results into increased cell area. Multilevel cell (MLC) structure paves a way to circumvent the problems related to the conventional STT/SOT based MTJ devices and provides enhanced integration density at reduced cost per bit. Conventional STT/SOT-MRAM requires a unit cell area of ~10-60 F2 and reported simulations have been based on available single-level MTJ compact models. However, till date no compact model exists that can capture the device physics of MLC-MTJ accurately. Hence, a novel compact model is proposed in this paper to capture the accurate device physics and behaviour of the MLC-MTJs. It is designed for MLCs with different MTJ configurations demonstrated so far, such as series and parallel free layer based MLC-MTJs. The proposed model is coded in Verilog-A, which is compatible with SPICE for circuit level simulations. The model is in close agreement with the experimental results exhibiting an average error of less than 15%.