Sanjeev B. Sathe

Natural convection arising from a heat generating substrate-mounted protrusion in a liquid-filled two-dimensional enclosure

Abstract An investigation of natural convection flow and heat transfer arising from a substrate-mounted protruding heat source immersed in a liquid-filled square enclosure is reported. The model considers heat transfer within the protrusion and substrate and the coupled natural convection in the fluid. Numerical predictions are obtained for a wide range of appropriate Rayleigh and Prandtl numbers and substrate to fluid thermal conductivity ratios that may be encountered in liquid-immersion cooling of electronic components. For many situations of interest prescribing simplistic heat transfer conditions at the solid surfaces is found inappropriate. Increasing the Rayleigh number beyond 106 and the substrate thermal conductivity beyond 100 times that of the liquid produces only a marginal decrease in the maximum temperatures. Computed protrusion surface temperatures compare favorably with available experimental results for a similar configuration.

Natural convection liquid immersion cooling of a heat source flush mounted on a conducting substrate in a square enclosure

Abstract A numerical investigation of natural convection flow and heat transfer due to a rectangular heat source flush mounted on a substrate in a liquid-filled square enclosure was conducted. A finite volume model that accounts for the coupled conduction within the substrate and heat source and the natural convection in the liquid was utilized for a wide range of Rayleigh and Prandtl numbers. Little reduction in maximum temperatures was observed when substrate to fluid and component to fluid thermal conductivity ratios were increased beyond 10 and 25, respectively. Computed temperatures using the present model compared favorably with an existing experimental study.

A numerical analysis of the thermal performance of single sided and back-to-back tape ball grid array packages

This paper presents the results of a comprehensive numerical study of the thermal performance of Tape Ball Grid Array package mounted on one side of a printed circuit board as well as packages mounted in back-to-back and offset configurations. A cover plate is attached to the back side of the chips to enhance heat transfer from the module. The assembled organic carrier is placed in a vertical channel. A conjugate heat transfer model is used which accounts for conduction in the packages and the card and convection in the surrounding air. The effect of location of the modules on a card with zero, one and two power planes is evaluated for thermal performance. Heat dissipation is studied for forced convection (2, 1, and 0.5 m/s). Comparison is made for single sided and back-to-back cases.

Parametric studies of the thermal performance of back-to-back tape ball grid array (TBGA) packages

This paper deals with parametric studies to evaluate the thermal performance of Tape Ball Grid Array (TBGA) packages mounted in back-to-back configurations onto organic printed circuit boards. A cover plate is attached to the back side of the chips to enhance heat transfer from the module. The assembled organic carrier is placed in a vertical channel. A conjugate heat transfer model is used which accounts for conduction in the packages and the card and convection in the surrounding air. The effect of location of the modules on a card with 0, 1 and 2 power planes is evaluated for thermal performance. Four different configurations of the TBGA modules on the card are investigated. Heat dissipation is studied for forced convection (2, 1, and 0.5m/s). The best performance resulted when the modules were placed at an offset. The bottom of the card is very useful for heat dissipation and blocking that heat transfer path by placing another TBGA on the back side is counter productive.

Void-effect modeling of flip-chip encapsulation on ceramic substrate

A detailed numerical and experimental study of the thermal-mechanical stress and strain in the C4 solder bumps of a flip chip ceramic chip carrier has been completed. The numerical model used was based upon the finite element method. The model simulated accelerated thermal cycling (ATC) from 0/spl deg/C to 100/spl deg/C. Several parametric studies were conducted, including the effects of chip size, micro-encapsulation, and the effect of the presence of voids in the micro-encapsulant. It was notably found that the presence of voids in the encapsulant does not significantly increase the stress/strain in the C4s, with the exception of very large voids and voids at or near the edge of the chip.