William L. Brodsky

Packaging design of the IBM system z10 enterprise class platform central electronic complex

The IBM System z10™ Enterprise Class mainframe addresses the modern data center requirements for minimizing floor space while increasing computing power efficiency. These objectives placed challenges on the z10™ packaging design as a result of significantly increased demand on system packaging density, power delivery, and logic and power cooling efficiency compared with the recent IBM System z9® and z990 mainframe generations. Several innovations were implemented to successfully meet these challenges: a more powerful multichip module (MCM) that delivers denser computing capability and a 64-way system; a vertically mated processor unit (PU) book structure that achieves a more efficient thermal implementation and a higher signal bandwidth between processors; and a PU book-centric dc-dc power delivery design that is more efficient. This paper presents the key elements to achieve this design: the novel mechanical load transmission paths and the connector technologies for the MCM, PU book, I/O, and power regulation components; an innovative cooling and thermal design that includes component-level tolerance of failures; and improved power delivery and power code developments to maximize the overall z10 compute efficiency.

Electronic packaging of the IBM z13 processor drawer

IBM z13 processor drawer W. D. Becker H. Harrer A. Huber W. L. Brodsky R. Krabbenhoft M. A. Cracraft D. Kaller G. Edlund T. Strach The electronic packaging of the IBM z13i is the foundation for a processor drawer that provides a significant increase in processing power relative to the IBM zEnterpriseA EC12 (zEC12) system while managing power and cost to meet the z13 product objectives. The z13 system architecture differs from previous high-end z Systemsi designs due to the introduction of a drawer-based processor design, organic single-chip modules (SCMs) in place of the ceramic MCMs (multi-chip modules), and a cabled interconnect between drawers in place of the PCB (printed circuit board) backplane of the zEC12. These innovations are coupled with next-generation signaling interfaces, providing a significant increase in signal bandwidth. The next-generation voltage regulation and decoupling provides the efficient power delivery needed to build a new processor subsystem with 40% more processor cores than the zEC12. The memory bandwidth and capacity have more than tripled, and the input/output bandwidth of the processor chip doubled to provide excellent scalability at the processor socket, drawer, and system level. The electronic packaging has been designed to meet all of these challenges, and this paper presents the design and integration of the electronic packaging of the z13 system.

Featured elastomer design for connector applications

This paper discusses a molded elastomeric structure that has been developed for use in connector applications. With the use of elastomeric materials, several challenges occur such as: dimensional stability for a grid of contacts as the elastomer member is compressed; contact force distribution across a grid of electrical contacts supported by a homogeneous molded elastomeric member constrained by boundary conditions; compressive stiffness of the elastomer and its ability to accommodate actuation tolerances within a contact force range; and structural stability of slender elastomeric features when used to increase the elastomeric structures compliancy. As connector I/O and densities increase, use of elastomeric materials with flexible circuits to replace metallic spring and conductor combinations is increasing. One advantage of this combination is the ability to arrange the contacts into dense arrays. In addition to the physical geometry, the component set offers several advantages to the electrical designer, dielectric constant, characteristic impedance, etc.<<ETX>>