Sarah K. Haney

A New Degradation Mechanism in High-Voltage SiC Power MOSFETs

The phenomenon of recombination-induced stacking faults in high-voltage p-n diodes in SiC has been previously shown to increase the forward voltage drop due to reduction of minority carrier lifetime. In this paper, it has been shown that, for the first time, this effect is equally important in unipolar devices such as high-voltage MOSFETs. If the internal body diode is allowed to be forward biased during the operation of these devices, then the recombination-induced SFs will reduce the majority carrier conduction current and increase the leakage current in blocking mode. The effect is more noticeable in high-voltage devices where the drift layer is thick and is not expected to impact 600-1200-V devices.

A 13 kV 4H-SiC n-Channel IGBT with Low Rdiff,on and Fast Switching

For the first time, high power 4H-SiC n-IGBTs have been demonstrated with 13 kV blocking and a low Rdiff,on of 22 mWcm2 which surpasses the 4H-SiC material limit for unipolar devices. Normally-off operation and >10 kV blocking is maintained up to 200oC base plate temperature. The on-state resistance has a slight positive temperature coefficient which makes the n-IGBT attractive for parallel configurations. MOS characterization reveals a low net positive fixed charge density in the oxide and a low interface trap density near the conduction band which produces a 3 V threshold and a peak channel mobility of 18 cm2/Vs in the lateral MOSFET test structure. Finally, encouraging device yields of 64% in the on-state and 27% in the blocking indicate that the 4H-SiC n-IGBT may eventually become a viable power device technology.

Inversion layer carrier concentration and mobility in 4H–SiC metal-oxide-semiconductor field-effect transistors

Free electron concentration and carrier mobility measurements on 4H–SiC metal-oxide-semiconductor inversion layers are reported in this article. The key finding is that in state-of-the-art nitrided gate oxides, loss of carriers by trapping no longer plays a significant role in the current degradation under heavy inversion conditions. Rather, it is the low carrier mobility (maximum∼60 cm2 V−1 s−1) that limits the channel current. The measured free carrier concentration is modeled using the charge-sheet model and the mobility is modeled by existing mobility models. Possible mobility mechanisms have been discussed based on the modeling results.

Critical Issues for MOS Based Power Devices in 4H-SiC

In this paper, we present the effects of MOS channel processing on the threshold voltage and the MOS field effect mobility of 4H-SiC MOSFETs. By increasing the p-well doping concentration by two orders of magnitude, the threshold voltage could be shifted positive from 0V to 5 V when a thermal oxide layer with NO post oxidation anneal was used as the gate dielectric layer. However, a severe degradation of MOS field effect mobility, decreasing from 37 cm2/Vs to 5 cm2/Vs, was also observed. Using a different processing technique, which uses a deposited oxide layer with an NO anneal, a threshold voltage of 7.5 V and a MOS field effect mobility of 15 cm2/Vs could be achieved. A 10 kV, 1 A power DMOSFET was demonstrated with this technique. A DMOSFET turn-off voltage of 5.25 V was measured at room temperature, which shifted to 3.0 V at 250oC, providing acceptable noise margins throughout the operating temperature range.

SiC MOSFET Reliability Update

Significant advancement has been made in the gate oxide reliability of SiC MOS devices to enable the commercial release of Cree’s Z-FET™ product. This paper discusses the key reliability results from Time-Dependent-Dielectric-Breakdown (TDDB) and High Temperature Gate Bias (HTGB) measurements that indicate that the SiC MOSFETs can demonstrate excellent lifetime and stable operation in the field.

Improved 4H-SiC MOS interfaces produced via two independent processes : Metal enhanced oxidation and 1300°C NO anneal

Two previously reported MOS processes, oxidation in the presence of metallic impurities and annealing in nitric oxide (NO), have both been optimized for compatibility with conventional 4H-SiC DMOSFET process technology. Metallic impurities are introduced by oxidizing in an alumina environment. This Metal Enhanced Oxidation (MEO) yields controlled oxide thickness (tOX) and robustness against high temperature processing and operation while maintaining high mobility (69 cm2/Vs) and near ideal NMOS C-V characteristics. Raising the NO anneal temperature from 1175oC to 1300oC results in a 67% increase in the mobility to 49 cm2/Vs with a slight stretch-out in the NMOS C-V. Both processes exhibit a small 30% mobility reduction in MOSFETs fabricated on NA = 1x1018 cm-3 implanted p-wells. The low field mobility in the MEO MOSFETs is observed to increase dramatically with measurement temperature to 160 cm2/Vs at 150oC.

Critical Technical Issues in High Voltage SiC Power Devices

In this paper, we review the state of the art of SiC switches and the technical issues which remain. Specifically, we will review the progress and remaining challenges associated with SiC power MOSFETs and BJTs. The most difficult issue when fabricating MOSFETs has been an excessive variation in threshold voltage from batch to batch. This difficulty arises due to the fact that the threshold voltage is determined by the difference between two large numbers, namely, a large fixed oxide charge and a large negative charge in the interface traps. There may also be some significant charge captured in the bulk traps in SiC and SiO2. The effect of recombination-induced stacking faults (SFs) on majority carrier mobility has been confirmed with 10 kV Merged PN Schottky (MPS) diodes and MOSFETs. The same SFs have been found to be responsible for degradation of BJTs.

Optimizing the thermally oxidized 4H-SiC MOS interface for P-channel devices

Optimization of the thermally oxidized 4H-SiC MOS interface has produced p-channel lateral MOSFETs with hole inversion layer mobility as high as 10 cm2/Vs. This has been accomplished by identifying the 1200oC Dry, 950oC Wet (un-nitrided) oxidation as ideal for hole conduction across the MOS inversion layer and by implant activation annealing at 1800oC of the heavily implanted n-type well. High temperature measurements show that the high mobility and normally-off operation is maintained throughout the operating temperature range. Oxide leakage measurements yield a dielectric strength of 8.5 MV/cm with 90% yield, thereby enabling the manufacture of high performance p-channel devices like the IGBT.

Status of 1200V 4H-SiC Power DMOSFETs

The commercial production of 1200 V 4H-SiC power MOSFETs is quickly becoming feasible in light of advances made in 4H-SiC substrate quality, improvements made in epitaxy, investigations of optimum device deign, advances made in increasing channel mobility with nitridation annealing, and optimization of device fabrication processes. These devices promise to enhance the efficiency of power handling circuits that currently rely on Si-based IGBTs. We routinely fabricate 1200 V power DMOSFETs with specific on-resistance (Ron(sp)) of 10 mOmega-cm² that show sub-microamps of leakage current at 1200 V with breakdown at greater than 1500 V. 1200V 4H-SiC DMOSFETs with active areas of 0.10 cm2 or 0.168 cm2 have been demonstrated for nominal current ratings of 10 A and 20 A, respectively.

Effect of Recombination-Induced Stacking Faults on Majority Carrier Conduction and Reverse Leakage Current on 10 kV SiC DMOSFETs

This paper presents the effect of recombination-induced stacking faults on the drift based forward conduction and leakage currents of high voltage 4H-SiC power devices. To show the effects, IV characteristics of a 4H-SiC 10 kV DMOSFET and a 4H-SiC 4 kV BJT have been evaluated before and after the induction of stacking faults in the drift epilayer. For both devices, significant increases in forward voltage drops, as well as marked increases in leakage currents have been observed. The results suggest that injection of minority carriers in majority carrier devices should be avoided at all times.