Fatima Husna

Characterization, Modeling, and Application of 10-kV SiC MOSFET

Ten-kilovolt SiC MOSFETs are currently under development by a number of organizations in the United States, with the aim of enabling their applications in high-voltage high-frequency power conversions. The aim of this paper is to obtain the key device characteristics of SiC MOSFETs so that their realistic application prospect can be provided. In particular, the emphasis is on obtaining their losses in various operation conditions from the extensive characterization study and a proposed behavioral SPICE model. Using the validated MOSFET SPICE model, a 20-kHz 370-W dc/dc boost converter based on a 10-kV 4H-SiC DMOSFET and diodes is designed and experimentally demonstrated. In the steady state of the boost converter, the total power loss in the 15.45-mm2 SiC MOSFET is 23.6 W for the input power of 428 W. The characterization study of the experimental SiC MOSFET and the experiment of the SiC MOSFET-based boost converter indicate that the turn-on losses of SiC MOSFETs are the dominant factors in determining their maximum operation frequency in hard-switched circuits with conventional thermal management. Replacing a 10-kV SiC PiN diode with a 10-kV SiC JBS diode as a boost diode and using a small external gate resistor, the turn-on loss of the SiC MOSFET can be reduced, and the 10-kV 5-A SiC MOSFET-based boost converter is predicted to be capable of a 20-kHz operation with a 5-kV dc output voltage and a 1.25-kW output power by the PSpice simulation with the MOSFET model. The low losses and fast switching speed of 10-kV SiC MOSFETs shown in the characterization study and the preliminary demonstration of the boost converter make them attractive in high-frequency high-voltage power-conversion applications.

A 13 kV 4H-SiC n-Channel IGBT with Low Rdiff,on and Fast Switching

For the first time, high power 4H-SiC n-IGBTs have been demonstrated with 13 kV blocking and a low Rdiff,on of 22 mWcm2 which surpasses the 4H-SiC material limit for unipolar devices. Normally-off operation and >10 kV blocking is maintained up to 200oC base plate temperature. The on-state resistance has a slight positive temperature coefficient which makes the n-IGBT attractive for parallel configurations. MOS characterization reveals a low net positive fixed charge density in the oxide and a low interface trap density near the conduction band which produces a 3 V threshold and a peak channel mobility of 18 cm2/Vs in the lateral MOSFET test structure. Finally, encouraging device yields of 64% in the on-state and 27% in the blocking indicate that the 4H-SiC n-IGBT may eventually become a viable power device technology.

10 kV SiC MOSFET Based Boost Converter

W kV SiC MOSFETs are currently under development by a number of organizations in the United States with the aim to enable their applications in high voltage high frequency power conversion applications. The aim of this study is to demonstrate their high frequency high temperature operation capability in the application of a DC/DC boost converter. A DC/DC boost converter based on a 10 kV 10 A SiC MOSFET and a 10 kV 5A Junction Barrier Schottky (JBS) diode is designed and tested for continuous conditions up to a switching frequency of 25 kHz, an output voltage of 4 kV, an output power of 4 kW and a junction temperature of 174degC for the SiC MOSFET. In the steady state of the 20 kHz boost converter operation, the input power is 4335 W, the output power is 4030 kW and the efficiency is 93%. The power loss analysis shows the total power loss in the 30.45 mm2 SiC MOSFET is 115 W, and the operating junction temperature of the SiC MOSFET is 140degC at the 20 kHz switching frequency. The power losses and the junction temperature of the SiC MOSFET as a function of the switching frequency, load current and input voltage in the boost converter are investigated extensively. The fast switching, low loss and high temperature operation capability of 10 kV SiC MOSFETs demonstrated in the DC/DC boost converter make them attractive in high frequency high voltage power conversion applications.

Performance of 60 A, 1200 V 4H-SiC DMOSFETs

Large area (8 mm x 7 mm) 1200 V 4H-SiC DMOSFETs with a specific on-resistance as low as 9 m•cm2 (at VGS = 20 V) able to conduct 60 A at a power dissipation of 200 W/cm2 are presented. On-resistance is fairly stable with temperature, increasing from 11.5 m•cm2 (at VGS = 15 V) at 25°C to 14 m•cm2 at 150°C. The DMOSFETs exhibit avalanche breakdown at 1600 V with the gate shorted to the source, although sub-breakdown leakage currents up to 50 A are observed at 1200 V and 200°C due to the threshold voltage lowering with temperature. When switched with a clamped inductive load circuit from 65 A conducting to 750 V blocking, the turn-on and turn-off energies at 150°C were less than 4.5 mJ.

4H-SiC bipolar junction transistors: From research to development - A case study: 1200 V, 20 A, stable SiC BJTs with high blocking yield

In this paper, for the first time, large area SiC BJTs were fabricated on SiC wafers with reduced Basal Plane Dislocations (BPDs). We have demonstrated: (1) stable performance on 1200 V, 20 A SiC BJTs after long duration of electrical stress at different current densities up to 150 A/cm2; (2) a blocking yield of ≫80% with low leakage current (≪20 nA at 1800 V) on 3″ wafers along with current gains in a range of 35–40. Both breakthroughs highlight the possibility for SiC BJTs to be commercialized and utilized in power electronics.

A Comparison of High Temperature Performance of SiC DMOSFETs and JFETs

High temperature characteristics of 4H-SiC power JFETs and DMOSFETs are presented in this paper. Both devices are based on pn junctions in 4H-SiC, and are capable of 300oC operation. The 4H-SiC JFET showed very predictable, well understood temperature dependent characteristics, because the current conduction depends on the drift of electrons in the bulk region, which is not restricted by traps in the MOS interface or at the pn junctions. On the other hand, in a 4H-SiC DMOSFET, electrons must flow through the MOS inversion layer with a very high interface state density. At high temperatures, the transconductance of the device improves and threshold voltage shifts negative because less electrons are trapped in the interface states, resulting in a much lower MOS channel resistance. This cancels out the increase in drift layer resistance, and as a result, a temperature insensitive on-resistance can be demonstrated. The performance of the two devices are compared, and a discussion of issues for their high temperature application is presented.

Improved 4H-SiC MOS interfaces produced via two independent processes : Metal enhanced oxidation and 1300°C NO anneal

Two previously reported MOS processes, oxidation in the presence of metallic impurities and annealing in nitric oxide (NO), have both been optimized for compatibility with conventional 4H-SiC DMOSFET process technology. Metallic impurities are introduced by oxidizing in an alumina environment. This Metal Enhanced Oxidation (MEO) yields controlled oxide thickness (tOX) and robustness against high temperature processing and operation while maintaining high mobility (69 cm2/Vs) and near ideal NMOS C-V characteristics. Raising the NO anneal temperature from 1175oC to 1300oC results in a 67% increase in the mobility to 49 cm2/Vs with a slight stretch-out in the NMOS C-V. Both processes exhibit a small 30% mobility reduction in MOSFETs fabricated on NA = 1x1018 cm-3 implanted p-wells. The low field mobility in the MEO MOSFETs is observed to increase dramatically with measurement temperature to 160 cm2/Vs at 150oC.

Effect of Recombination-Induced Stacking Faults on Majority Carrier Conduction and Reverse Leakage Current on 10 kV SiC DMOSFETs

This paper presents the effect of recombination-induced stacking faults on the drift based forward conduction and leakage currents of high voltage 4H-SiC power devices. To show the effects, IV characteristics of a 4H-SiC 10 kV DMOSFET and a 4H-SiC 4 kV BJT have been evaluated before and after the induction of stacking faults in the drift epilayer. For both devices, significant increases in forward voltage drops, as well as marked increases in leakage currents have been observed. The results suggest that injection of minority carriers in majority carrier devices should be avoided at all times.

High Temperature DC-DC Converter Performance Comparison Using SiC JFETs, BJTs and Si MOSFETs

The performance and characterization of SiC JFETs and BJTs, used as inverter switching devices, in a 2 kW, high temperature, 33 kHz, 270-28 V DC-DC converter has been accomplished. SiC and Si power devices were characterized in a phase shifted H-bridge converter topology utilizing novel high temperature powdered ferrite transformer material, high temperature ceramic filter capacitors, SiC rectifiers, and 10 oz. 220oC polyimide printed circuit boards. The SiC devices were observed to provide excellent static and dynamic characteristics at temperatures up to 300oC. SiC JFETs were seen to exhibit on-resistance trends consistent with temperature-mobility kinetics and temperature invariant dynamic loss characteristics. SiC BJTs exhibited positive temperature coefficients (TCE) of VCE and negative β TCEs, with only a 2-fold increase in on-resistance at 300oC. Both SiC power devices possessed fast inductive switching characteristics with τon and τoff ~100-150 ns when driving the transformer load. The SiC converter characteristics were compared to Si-MOSFET H-bridge operation, over its functional temperature range (30-230oC), and highlights the superiority of SiC device technology for extreme environment power applications.

First Demonstration of 2.1 kW Output Power at 425 MHz Using 4H-SiC RF Power BJTs

For the first time, 4H-SiC RF bipolar junction transistors have been used to produce an output power in excess of 2.1 kW at 425 MHz. For an input pulse width of 2 μs and 1% duty cycle, the power gain at peak output power is 6.3 dB with the collector efficiency and power added efficiency [PAE] being 45% and 35%, respectively, at a collector supply voltage of 75 V in a class C configuration. The package consists of 24 cells (2 chips) having an emitter periphery of approximately 1 inch per cell. Each cell produced a DC current gain (β) of 15 and a common emitter breakdown voltage (BVCEO) greater than 250 V. A peak output power of 87 W per cell was obtained at 425 MHz, as compared to the earlier report of 50 W per cell [1, 2] by using a shorter pulse width and duty cycle.