Sarah Olsen

A model for capacitance reconstruction from measured lossy MOS capacitance-voltage characteristics

A capacitance model is developed and a correction formula is derived to reconstruct the intrinsic oxide capacitance value from measured capacitance and conductance of lossy MOS devices. Due to discrepancies during processing, such as cleaning, an unwanted lossy dielectric layer is present in the oxide/semiconductor interface causing the measured capacitance in strong accumulation to be frequency dependent. The capacitance–voltage characteristics after correction are free from any frequency dispersion effect and give the actual oxide thickness in accumulation at all frequencies. Simulation of the measured capacitance–frequency curve was carried out using the model. The model was applied to SiO2/Si, SiO2/strained Si and GaO2/GaAs MOS capacitors.

Impact of strained-Si thickness and Ge out-diffusion on gate oxide quality for strained-Si surface channel n-MOSFETs

Surface channel strained-silicon MOSFETs on relaxed Si/sub 1-x/Ge/sub x/ virtual substrates (VSs) have been established as an attractive avenue for extending Si CMOS performance as dictated by Moores law. The performance of a surface channel Si n-MOSFET is significantly influenced by strained Si/SiO/sub 2/ interface quality. The effects of Ge content (20, 25, and 30%) in the VS and strained-Si thickness (6, 5.5, 4.7, and 3.7 nm) on the strained Si/SiO/sub 2/ interface have been investigated. The interface trap density was found to be proportional to the Ge content in the VS. Fixed oxide charge density reduces to a lower limit at higher strained-Si thickness for any Ge content in the VS, and the value increases as the strained-Si thickness is reduced. There is a high concentration of interface trap charge and fixed oxide charge present for devices with a strained-Si channel thickness below 4.7 nm. To investigate the effect of strained Si/SiO/sub 2/ interface quality on MOSFET devices fabricated using a high-temperature CMOS process, the performance of surface channel n-MOSFETs has been correlated with channel thickness. It is noted that the drain-current rapidly decreases at low gate voltages for channel thicknesses less than 4.7 nm. The performance of both MOS capacitors and MOSFETs degraded below a strained-Si thickness of 4.7 nm irrespective of the Ge content in the VS even up to 30%. TCAD simulations have been carried out to analyze the effect of strained Si/SiO/sub 2/ interface on electrical characteristics. Performance degradation in thin strained-Si channels is primarily attributed to gate oxide quality. The out-diffused Ge accumulates at the strained Si/SiO/sub 2/ interface, introducing a significant amount of interface traps and fixed oxide charges during thermal oxidation. Interface trap density and fixed oxide charge density significantly increased when the Ge concentration at the surface becomes more than 6%. This paper suggests that a minimum strained-Si layer thickness of /spl sim/ 5.0 nm is required to achieve a good strained Si/SiO/sub 2/ interface quality for surface channel strained-Si n-MOSFETs, fabricated using a high thermal budget CMOS process.

High-performance nMOSFETs using a novel strained Si/SiGe CMOS architecture

Performance enhancements of up to 170% in drain current, maximum transconductance, and field-effect mobility are presented for nMOSFETs fabricated with strained-Si channels compared with identically processed bulk Si MOSFETs. A novel layer structure comprising Si/Si/sub 0.7/Ge/sub 0.3/ on an Si/sub 0.85/Ge/sub 0.15/ virtual substrate (VS) offers improved performance advantages and a strain-compensated structure. A high thermal budget process produces devices having excellent on/off-state drain-current characteristics, transconductance, and subthreshold characteristics. The virtual substrate does not require chemical-mechanical polishing and the same performance enhancement is achieved with and without a titanium salicide process.

RF Extraction of Self-Heating Effects in FinFETs

Multigate semiconductor devices are celebrated for improved electrostatic control and reduced short-channel effects. However, nonplanar architectures suffer from increases of access resistances and capacitances, as well as self-heating effects due to confinement and increased phonon boundary scattering. In silicon-on-insulator (SOI) technology, the self-heating effects are aggravated by the presence of a thick buried oxide with low thermal conductivity, which prevents effective heat removal from the device active region to the Si substrate. Due to the shrinking of device dimensions in the nanometer scale, the thermal time constant that characterizes the dynamic self-heating is significantly reduced, and radio frequency extraction techniques are needed. The dynamic self-heating effect is characterized in n-channel SOI FinFETs, and the dependence of thermal resistance on FinFET geometry is discussed. It is experimentally confirmed that the fin width and the number of parallel fins are the most important parameters for thermal management in FinFETs, whereas fin spacing plays a less significant role.

The High-Mobility Bended n-Channel Silicon Nanowire Transistor

This work demonstrates a method for incorporating strain in silicon nanowire gate-all-around (GAA) n-MOSFETs by oxidation-induced bending of the nanowire channel and reports on the resulting improvement in device performance. The variation in strain measured during processing is discussed. The strain profile in silicon nanowires is evaluated by Raman spectroscopy both before device gate stack fabrication (tensile strains of up to 2.5% are measured) and by measurement through the polysilicon gate on completed electrically characterized devices. Drain current boosting in bended n-channels is investigated as a function of the transistor operation regime, and it is shown that the enhancement depends on the effective electrical field. The maximum observed electron mobility enhancement is on the order of 100% for a gate bias near the threshold voltage. Measurements of stress through the full gate stack and experimental device characteristics of the same transistor reveal a stress of 600 MPa and corresponding improvements of the normalized drain current, normalized transconductance, and low-field mobility by 34% (at maximum gate overdrive), 50% (at g max), and 53%, respectively, compared with a reference nonstrained device at room temperature. Finally, it is found that, at low temperatures, the low-field mobility is much higher in bended devices, compared with nonbended devices.

Bended Gate-All-Around Nanowire MOSFET: a device with enhanced carrier mobility due to oxidation-induced tensile stress

In this paper we investigate the mobility enhancement due to strain in bended NW MOSFETs. Stress of 200 MPa to 2 GPa, induced by thermal oxidation, is measured in suspended NW FETs by Raman spectroscopy. Mobility enhancement of more than 100% is observed. Performance gain of bended compared to non-bended structures is most pronounced in low field conditions and at low temperatures.

Strained Si/SiGe n-channel MOSFETs: impact of cross-hatching on device performance

The performance of surface channel MOSFET devices depends on the Si/SiO2 interface quality. The present study has examined the Si/SiO2 interface of strained Si n-channel MOSFETs fabricated on a Si/SiGe virtual substrate. Evidence of a variation in the oxidation rate of strained Si along the cross-hatch period is presented. The undulating oxide thickness was found to be accompanied by increased nanoscale roughness at the Si/SiO2 interface for the strained Si surface channel devices compared with conventional MOSFETs. Fluctuations in the strained Si surface channel thickness were additionally caused by the variation in oxidation rate. The control devices exhibited a tighter distribution of electrical characteristics than the strained Si devices due to the non-uniform cross-hatch severity across the Si/SiGe wafer. The results provide strong evidence that significantly enhanced performance of HNMOS surface channel devices is possible through optimization of epitaxial growth methods. Strain in the channel was maintained following device fabrication using a conventional process with a reduced thermal budget.

Study of strain relaxation in Si/SiGe metal-oxide-semiconductor field-effect transistors

We report a study of strained Si metal-oxide-semiconductor field-effect transistors (MOSFET’s) fabricated using a high thermal budget. The impact of Si channel strain on MOSFET performance, leakage current, and yield is investigated for Si1−xGex virtual substrates having Ge compositions varying from 0% to 30%. Increasing the Ge fraction in the SiGe virtual substrate increases the amount of tensile strain in the Si layer and consequently increases the electron mobility. High levels of strain, however, reduce the critical thickness of strained Si, above which Si becomes metastable and susceptible to relaxation during high-temperature device fabrication. Increasing the Ge composition in the virtual substrate up to 30% is shown to result in significant enhancements in MOSFET drain current and transconductance due to increased strain in the device channels. However, cross-wafer electrical yield data as a function of Ge composition are reported and show that increasing Ge compositions above 15% simultaneously r...

Study of single- and dual-channel designs for high-performance strained-Si-SiGe n-MOSFETs

Results comparing strained-Si-SiGe n-channel MOSFET performance of single-and dual-surface channel devices fabricated using 15% Ge content SiGe virtual substrates are presented. Device fabrication used high thermal budget processes and virtual substrates were not polished. Mobility enhancement factors exceeding 1.6 are demonstrated for both single-and dual-channel device architectures compared with bulk-Si control devices. Single-channel devices exhibit improved gate oxide quality, and larger mobility enhancements, at higher vertical effective fields compared with the dual-channel strain-compensated devices. The compromised performance enhancements of the dual-channel devices are attributed to greater interface roughness and increased Ge diffusion resulting from the Si/sub 0.7/Ge/sub 0.3/ buried channel layer.

C–V characterization of strained Si/SiGe multiple heterojunction capacitors as a tool for heterojunction MOSFET channel design

Capacitance–voltage (C–V) characteristics are used to investigate double heterojunction strained Si/SiGe MOS capacitors. Structures of this type potentially form the channels of CMOS devices based on the strained Si/SiGe material system. The technique represents a fast and non-destructive method to determine important characteristics such as layer thicknesses, threshold voltages and band offsets. Moreover, it contributes to the design of optimum heterostructures for CMOS. Experimental C–V data are compared with simulation and complementary results including SIMS and TEM to confirm the accuracy of the technique.