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Dive into the research topics where Satohiko Hoshino is active.

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Featured researches published by Satohiko Hoshino.


Journal of Vacuum Science & Technology. B. Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena | 2017

Near-infrared laser annealing of Ge layers epitaxially grown on Si for high-performance photonic devices

Sho Nagatomo; Yasuhiko Ishikawa; Satohiko Hoshino

Near-infrared laser annealing of Ge epitaxial layers on Si is studied as a postgrowth annealing process to reduce the density of threading dislocations (TDs) in Ge. Laser annealing is performed using an exposure of 1.07-μm-laser light with the power density as large as 8 kW/cm2 and the duration as short as 10 ms. The TD density is successfully reduced from 6 × 108 to 2 × 108 cm−2 in a 600-nm-thick Ge layer grown by ultrahigh-vacuum chemical vapor deposition on Si. Vertical pin photodetectors of laser-annealed Ge show a significant reduction of dark leakage current as small as 20 mA/cm2 with a high photodetection efficiency. The short annealing time is effective to prevent the dopant diffusion in Ge together with the Ge-Si intermixing at the interface, being applicable to the annealing even after the formation of pin junctions in Ge. In terms of the reduction of thermal budget, the use of longer wavelength up to ∼1.6 μm has potential applications to preferential annealing of Ge layers on a Si platform due ...


conference on lasers and electro optics | 2016

Accuracy enhancement of sub-mm chip self-alignment using liquid surface tension for hybrid integration

Shinya Kikuta; Satohiko Hoshino; Yoshiki Yamanishi; Takafumi Fukushima; Kang Wook Lee; Mitsumasa Koyanagi

A self-alignment process of sub-mm chips is studied for hybrid integration toward silicon photonics applications. Capillary forces by liquid surface tension drive the tiny chips to precisely and quickly align on silicon wafers. Self-alignment behaviors and the resulting high accuracies of the sub-mm chips are discussed in this work.


2014 International Conference on Solid State Devices and Materials | 2014

Impact of Post-Growth Annealing for Thin-Film Ge Photodiodes on Si

Sho Nagatomo; Y. Kawamata; Y. Izawa; Satohiko Hoshino; Yasuhiko Ishikawa

Effect of post-growth annealing is studied for thin-film (200 600 nm) Ge pin photodiodes on Si. High-temperature post-growth annealing in a furnace (≥ 800°C) can suppress the dark leakage current, while the detection efficiency for near-infrared light is degraded, resulting from the alloying of Ge film with Si. A laser annealing is demonstrated to prevent such a SiGe formation.


Archive | 2009

Selective deposition of metal-containing cap layers for semiconductor devices

Tadahiro Ishizaka; Shigeru Mizuno; Satohiko Hoshino; Hiroyuki Nagai; Yuki Chiba; Frank M. Cerio


Archive | 2007

Diffusion barrier for integrated circuits formed from a layer of reactive metal and method of fabrication

Tadahiro Ishizaka; Satohiko Hoshino; Kuzuhiro Hamamoto; Shigeru Mizuno; Yasushi Mizusawa


Archive | 2003

Semiconductor manufacturing method and semiconductor manufacturing apparatus

Satohiko Hoshino; Shingo Hishiya


Archive | 2006

Forming method of low dielectric constant insulating film of semiconductor device, semiconductor device, and low dielectric constant insulating film forming apparatus

Shinji Ide; Masaru Sasaki; Satohiko Hoshino


Archive | 2004

Fabrication of low dielectric constant insulating film

Masaru Sasaki; Satohiko Hoshino; Shinji Ide; Yusaku Kashiwagi


Archive | 2004

Method of forming low-permittivity insulation film of semiconductor device, semiconductor device using the method and low-permittivity insulation film forming device

Shinji Ide; Masaru Sasaki; Satohiko Hoshino


Archive | 2003

Method for forming insulating layer

Toshiaki Hongoh; Satohiko Hoshino

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