Satoru Kuramochi

A Characterized Redistribution Layer Architecture for Advanced Packaging Technologies

An enhanced redistribution layer architecture has been developed in which the Cu wires are directly covered with a double layer consisting of two types of dielectrics by using a semi-additive process. The double layer enhanced the thermal and electrical reliabilities of the Cu wires. Moreover, it enabled fabrication of a single-sided nine-level redistribution layer embedded with a fully stacked via. This greatly increased wiring layout flexibility and enhanced the transmission rate. Characterization of this architecture revealed that it has several advantages for advanced packaging technologies including a 2.5D interposer.

Demonstration of High Electrical Reliability of Sub-2 Micron Cu Traces Covered with Inorganic Dielectrics for Advanced Packaging Technologies

Aggressive scaling down of the Cu trace pitch in the redistribution layer (RDL) is needed to meet the design rule for high-density I/O used in advanced packaging. Such a downsized RDL, however, will be vulnerable to voltage and current stresses, in addition to environmental stress. Voltage stress, for example, degrades the reliability of electrical isolation (dielectric strength). This will likely be a serious problem when the pitch of the Cu traces becomes less than 4 µm since Cu migration will become substantial due to a rapid increase in the electric field between traces. This means that the conventional RDL structure based on a semi-additive process may fail to meet the performance specified by the Joint Electron Device Engineering Council (JEDEC) reliability standard. A previously proposed enhanced RDL, in which the Cu traces are covered with two types of inorganic dielectrics, showed potential performance suitable for advanced packaging technologies in terms of both electrical and mechanical reliability. The Cu trace pitch has now been scaled down from 20 µm to as small as 2 µm. Characterization of this downsized redistribution layer in terms of electrical reliability using biased highly accelerated temperature and humidity stress testing and electromigration testing showed that the first inorganic dielectric completely suppressed Cu migration and Cu surface diffusion, which degrade electrical isolation and electromigration resistance, respectively. This downsized enhanced RDL is thus promising for advanced high-density fan-out wafer-level packaging and 2.5 D interposer packaging.

Board-Level Reliability of 3D through Glass via Filters During Thermal Cycling

This paper theoretically and experimentally assesses the board-level reliability of glass-based 3D Integrated Passive Device (IPD) with TGV-based inductor capacitor (LC) filters in thermal cycling test. Important failure modes such as wellknown solder joint cracking and TGV failure as well as other failure modes such as glass cratering are investigated in this work. Through finite-element modeling, initial reliability predictions are made using a Morrow-Darveaux approach for solder fatigue life. To predict glass cratering, a stress-based approach is used. In the second part of this work, reliability experiments are conducted on fabricated samples, demonstrating reliable 3D IPD glass packages. Failure analysis has found that solder joint cracking and glass cratering have occurred, but no TGV failures have occurred. The experimental results are also compared to numerical predictions. Then, for future designs, the models are used to analyze the impact of key material and design parameters on the experimentally observed failure modes. It is predicted that reducing the glass core thickness will improve solder fatigue life and help prevent glass cratering. Also, TGVs are recommended to be kept away from solder joints to prevent glass cratering. Stress buffering of the dielectric also improves the reliability, though less than glass core thickness. By developing and correlating a model specifically for these devices, this work, for the first time, enables accurate study and optimization of key design parameters for 3D glass IPD radio frequency (RF) devices to achieve high mechanically reliability, high-performance long term evolution band devices, with potentially smaller footprint and thickness compared to current LTCC counterparts.

TGV (Thru-Glass Via) Metallization by Direct Cu Plating on Glass

Conformal coating or solid-filling metallization on TGV glass with the highly conductive thick Cu is desired to enhance the performance for high-frequency electronic devices in the IoT era due to the outstanding RF properties of the glass and high-Q nature of thick Cu metallization on glass. Previously, metallization on the glass with sputtering and printing technology has been demonstrated. However, there are some concerns in terms of throughput and mechanical integrity of sputter seed layer for Cu metallization on TGV sidewalls and the smooth glass surfaces. This study reports our novel metallization technology to obtain good adhesion without degrading the RF performance associated with glass properties and Cu conductivity. Metal circuits including high-Q RF inductors were created by wet direct plating process with semi-additive process, achieved without any roughening the surface of glass substrate or TGV sidewall. Surface cleaning is critical to obtain good adhesion. In this experiment, glass surface was cleaned by the irradiation of UV light and alkaline degreasing with complex agent. UV light and alkaline degreasing make the surface of the glass clean and Cu adhesion to glass improves with minimal stress to the glass itself. Through this work, Cu to glass adhesion strength of 0.35kN/m has been achieved. Using this method, we have successfully demonstrated direct cupper plating on TGV holes and glass surfaces with semi-additive processing (SAP) and conformal plating for RF front end filters with better performance. This technology further optimized for high-performance RF standalone passive network and RF interposers with the capability of thick (15um) Cu plating directly on TGV glass for the first time in 8 inch diameter x 0.35mm thick wafer format. This direct plating technology is scalable to panel sizes, targeting low-cost and high-throughput TGV metallization.

Electroless and Electrolytic Copper Plating of Glass Interposer Combined with Metal Oxide Adhesion Layer for Manufacturing 3D RF Devices

High performance radio frequency (RF) front end filters were fabricated using glass interposer and 3D packaging technologies, especially through glass vias (TGV) and direct Cu metallization on the glass. Major challenges for the use of TGV in RF and electronics applications are the cost competitiveness, high throughput and reliable metallization of both TGV and flat glass surface with an excellent adhesion. In this study, a thin metal oxide adhesion promotion layer (about 8-9 nm) called VitroCoat layer is dip-coated by a modified sol-gel process followed by sintering which creates chemical bonds to the glass. Sol-gel dip coating process has good coating uniformity on both TGV and top surface under optimized coating conditions. Uniform coating can be achieved on minimum 30 μm diameter TGVs on a 300 μm thick and 200 mm diameter glass wafers. The thin adhesive layer enables electroless and electrolytic copper plating directly onto glass substrates without impacting high frequency performance. Excellent adhesion of electroless plated copper seed layer on glass can be achieved by using the adhesive layer and annealing technology. The thin adhesive layer is non-conductive and can be easily removed from the area between circuit traces during electroless copper seed layer etching. We have successfully integrated the adhesion layer and electroless and electrolytic copper plating technologies into semi-additive process (SAP) and built up a 3D RF front end filter devices on 400 μm thick 200mm diameter glass wafers as well as 300mm x 300mm glass panels with 80 μm diameter holes.