Miyuki Akazawa

Development of 300 mm TSV interposer with redistribution layers on both sides using MEMS processes

A Silicon interposer with through silicon via (TSV) has become important key components of 3D integration. It is used as an intermediate carrier and a wiring device for IC components like logics, memories, sensors, and so on. Due to wiring with custom design on front and back side, a TSV interposer enables to adapt the fine pitch IO terminals of the mounted ICs to the IO geometries of the package level. However the key problem facing the TSV interposer is a cost issue. In this paper, TSV based interposer fabrication process for 3D packaging has been presented and the process uniformity with 300 mm wafer was evaluated for cost reduction and yield improvement. TSVs of 50 μm in diameter were formed on a 300 mm wafer of 500 μm in thickness by deep reactive ion etching (DRIE) process and the vias were isolated with SiO2 layer, followed by barrier/seed layers of Ti/Cu deposition. The TSVs were filled with solid Copper (Cu) using electroplating of optimized periodic pulse reverse (PPR) and chemical mechanical polishing (CMP) process also developed to remove the Cu overburden. For void free TSV interconnects and uniformity improvement, the Cu electroplating process was simulated with 300 mm wafer and developed with the simulation result. The process uniformity of Cu electroplating was equivalent to the simulation result and void free TSV interconnects were successfully formed. The RDL lines were formed on the TSV by Cu electroplating and the RDL lines were electrically isolated with the dielectric PBO film. The TSV interposer of 500 μm thickness has been fabricated successfully with MEMS processes and the vias were in good conductivity from the top to the bottom. The distribution of via etching process, via filling process and CMP process were evaluated and no significant failures were observed. The uniformity of the via etching process was less than 5 %. The distribution of Cu overburden thickness was less than 100 μm. The dishing amount of Cu via after CMP was less than 10 μm. The electric characteristics of RDL leakage current and via resistance were measured. The leakage current between RDL lines was about 10-9 A so that the RDL lines were electrically isolated. The average value of via resistances was 2.43 ohm and via resistances were normally distributed with tangible electric characteristics. The fabrication process of TSV based silicon interposer with 300 mm wafer by MEMS processes was successfully demonstrated in terms of mass production.

A Characterized Redistribution Layer Architecture for Advanced Packaging Technologies

An enhanced redistribution layer architecture has been developed in which the Cu wires are directly covered with a double layer consisting of two types of dielectrics by using a semi-additive process. The double layer enhanced the thermal and electrical reliabilities of the Cu wires. Moreover, it enabled fabrication of a single-sided nine-level redistribution layer embedded with a fully stacked via. This greatly increased wiring layout flexibility and enhanced the transmission rate. Characterization of this architecture revealed that it has several advantages for advanced packaging technologies including a 2.5D interposer.

Electroless and Electrolytic Copper Plating of Glass Interposer Combined with Metal Oxide Adhesion Layer for Manufacturing 3D RF Devices

High performance radio frequency (RF) front end filters were fabricated using glass interposer and 3D packaging technologies, especially through glass vias (TGV) and direct Cu metallization on the glass. Major challenges for the use of TGV in RF and electronics applications are the cost competitiveness, high throughput and reliable metallization of both TGV and flat glass surface with an excellent adhesion. In this study, a thin metal oxide adhesion promotion layer (about 8-9 nm) called VitroCoat layer is dip-coated by a modified sol-gel process followed by sintering which creates chemical bonds to the glass. Sol-gel dip coating process has good coating uniformity on both TGV and top surface under optimized coating conditions. Uniform coating can be achieved on minimum 30 μm diameter TGVs on a 300 μm thick and 200 mm diameter glass wafers. The thin adhesive layer enables electroless and electrolytic copper plating directly onto glass substrates without impacting high frequency performance. Excellent adhesion of electroless plated copper seed layer on glass can be achieved by using the adhesive layer and annealing technology. The thin adhesive layer is non-conductive and can be easily removed from the area between circuit traces during electroless copper seed layer etching. We have successfully integrated the adhesion layer and electroless and electrolytic copper plating technologies into semi-additive process (SAP) and built up a 3D RF front end filter devices on 400 μm thick 200mm diameter glass wafers as well as 300mm x 300mm glass panels with 80 μm diameter holes.

Glass interposer technology advances for high density packaging

As electronic product becomes smaller and lighter with an increasing number of function, the demand for high density and high integration becomes stronger. Interposers for system in package will became more and more important for advanced electronic systems. Silicon interposers with through silicon vias (TSV) and back end of line (BEOL) wiring offer compelling benefits for 2.5D and 3D system integration; however, they are limited by high cost and high electrical loss. On the other hand, glass has many properties that make it an ideal substrate for interposer substrates such as; ultra high resistivity, adjustable thermal expansion (CTE) and manufacturability with large panel size. Furthermore, glass via formation capabilities have dramatically improved over the past several years. Fully populated wafers with >100,000 through holes (50μm diameter) are fabricated today with 300μm thick glass. This paper presents the demonstration of glass interposers with fine pitch metalized through via. The application of glass interposer to 2.5D integration of multiple chips requires ultra-fine line and space. A semi-additive process consisting of copper seed layer deposition, photolithography, and electrolytic copper pattern plating used for RDL. High frequency transmission characteristics were measured with TGV co planer wave guide. Twin types of Cu plating method with through via, full filling plating and conformal plating are compared with process capability using X ray observation. Glass interposer with conformal plated via demonstrated on 300mm panel format. Electrical characteristics are measured with daisy chain test elementary vehicle. Excellent through via reliability was demonstrated at 200um pitch passed 1000 cycle from -40 cereuses deg to 80 cereuses deg.

Glass interposer for advanced packaging solution

As electronic product becomes smaller and lighter with an increasing number of function, the demand for high density and high integration becomes stronger. Interposers for system in package will became more and more important for advanced electronic systems. Silicon interposers with through silicon vias (TSV) and back end of line (BEOL) wiring offer compelling benefits for 2.5D and 3D system integration; however, they are limited by high cost and high electrical loss. On the other hand, glass has many properties that make it an ideal substrate for interposer substrates such as; ultra high resistivity, adjustable thermal expansion (CTE) and manufacturability with large panel size. Furthermore, glass via formation capabilities have dramatically improved over the past several years. Fully populated wafers with >100,000 through holes (50μm diameter) are fabricated today with 300μm thick glass. This paper presents the demonstration of glass interposers with fine pitch metalized through via. The application of glass interposer to 2.5D integration of multiple chips requires ultra-fine line and space. A semi-additive process consisting of copper seed layer deposition, photolithography, and electrolytic copper pattern plating used for RDL. High frequency transmission characteristics were measured with TGV co planer wave guide. Twin types of Cu plating method with through via, full filling plating and conformal plating are compared with process capability using X ray observation. Glass interposer with conformal plated via demonstrated on 300mm panel format. Electrical characteristics are measured with daisy chain test elementary vehicle. Excellent through via reliability was demonstrated at 200um pitch passed 1000cycle from -40 cereuses deg to 80 cereuses deg.