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Dive into the research topics where Satoshi Hatsukawa is active.

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Featured researches published by Satoshi Hatsukawa.


Materials Science Forum | 2014

Blocking Characteristics of 2.2 kV and 3.3 kV-Class 4H-SiC MOSFETs with Improved Doping Control for Edge Termination

Keiji Wada; Kosuke Uchida; Ren Kimura; Mitsuhiko Sakai; Satoshi Hatsukawa; Kenji Hiratsuka; Noriyuki Hirakata; Yasuki Mikamura

Blocking characteristics of 2.2 kV and 3.3 kV -class 4H-SiC MOSFETs with various doping conditions for the edge termination region have been investigated. By optimizing the implanted dose into the edge termination structure consisting of junction termination extension (JTE) and field limiting ring (FLR), a breakdown voltage of 3,850 V for 3.3 kV -class MOSFET has been attained. This result corresponds to about 95% of the approximate parallel-plane breakdown voltage estimated from the doping concentration and the thickness of the epitaxial layer. Implanted doping for the JFET region is effective in reducing JFET resistance, resulting in the specific on-resistance of 14.2 mΩcm2 for 3.3 kV SiC MOSFETs. Switching characteristics at the high drain voltage of 2.0 kV are also discussed.


Materials Science Forum | 2016

Newly Developed Switching Analysis Method for 3.3 kV 400 a Full SiC Module

Satoshi Hatsukawa; Shigenori Toyoshima; Takashi Tsuno; Yasuki Mikamura

We have demonstrated a new analysis method using a precise equivalent circuit of 3.3 kV 400 A full SiC modules and showed that the calculated waveforms well agree with the measured waveforms. We have also examined the current distribution in the module by utilizing this equivalent circuit model.


Materials Science Forum | 2006

Low On-Resistance in 4H-SiC RESURF JFETs Fabricated with Dry Process for Implantation Metal Mask

Takeyoshi Masuda; Kazuhiro Fujikawa; Kaoru Shibata; Hideto Tamaso; Satoshi Hatsukawa; Hitoki Tokuda; Akihiko Saegusa; Yasuo Namikawa; Hideki Hayashi

We fabricated 4H-SiC lateral JFETs with a reduced surface field (RESURF) structure, which can prevent the concentration of electric field at the edge of the gate metal [1]. Previously, we reported on the 4H-SiC RESURF JFET with a gate length (LG) of 10 μm [2]. Its specific on-resistance was 50 mΩcm2, which was still high. Therefore, a Ti/W layer was used as an ion implantation mask so as to decrease the thickness of the mask and to improve an accuracy of the device process. A RESURF JFET with the gate length (LG) of 3.0 μm was fabricated, and the specific on-resistance of 6.3 mΩcm2 was obtained. In this paper, the fabrication process and the electrical characteristics of the device are described.


Materials Science Forum | 2013

PWM Power Supply Using SiC RESURF JFETs with High Speed Switching

Satoshi Hatsukawa; Takashi Tsuno; Kazuhiro Fujikawa; Nobuo Shiga; Tuya Wuren; Kazuyuki Wada; Takashi Ohira

400V/2.5A 4H-SiC JFETs, having a reduced surface field (RESURF) structure have been fabricated. Measurements on the on-resistance, blocking, and switching characteristics were carried out. It was confirmed that the JFET has fast switching characteristics. A demonstration of a Pulse Width Modulation (PWM) decoder using JFETs was carried out. The input waveform, which is pulse width modulated 20.5MHz at 4.1MHz sine wave, as able to be decoded at 4.1MHz sine wave.


Materials Science Forum | 2007

Fabrication of a multi-chip module of 4H-SiC RESURF-type JFETs

Hideto Tamaso; Jiro Shinkai; Takashi Hoshino; Hitoki Tokuda; Kenichi Sawada; Kazuhiro Fujikawa; Takeyoshi Masuda; Satoshi Hatsukawa; Shin Harada; Yasuo Namikawa

We fabricated a multi-chip module of 4H-SiC reduced surface field (RESURF)-type lateral JFETs. A single chip consists of 4 unit devices of 2.0 mm × 0.5 mm in size, which were isolated electrically from each other. The multi-chip module consists of 8 chips mounted on an AMC substrate. The drain current and the breakdown voltage of the module are over 3 A and 771 V, respectively. The turn-on time and the turn-off time are 36ns and 166ns, respectively. The module resistance is proportional to the absolute temperature to the 1.05th power.


Archive | 2003

Vertical junction field effect transistor and method for fabricating the same

Takashi Hoshino; Shin Harada; Kazuhiro Fujikawa; Satoshi Hatsukawa; Kenichi Hirotsu


european conference on power electronics and applications | 2009

HF gate drive circuit for a normally-on SiC JFET with inherent safety

Tsuguhiro Takuno; Takashi Hikihara; Takashi Tsuno; Satoshi Hatsukawa


Archive | 2007

Vertical junction field effect transistors, and methods of producing the vertical junction field effect transistors

Takashi Hoshino; Shin Harada; Kazuhiro Fujikawa; Satoshi Hatsukawa; Kenichi Hirotsu


Archive | 2010

Power line communication device, power supply circuit with communication function, electric appliance, and control and monitoring system

Takashi Hikihara; Tsuguhiro Takuno; Kenichi Hirotsu; Takefumi Shimoguchi; Toshikazu Shibata; Takashi Tsuno; Satoshi Hatsukawa


Archive | 2009

Lateral junction field effect transistor and method of manufacturing the same

Kazuhiro Fujikawa; Shin Harada; Kenichi Hirotsu; Satoshi Hatsukawa; Takashi Hoshino; Hiroyuki Matsunami; Tsunenobu Kimoto

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Kazuhiro Fujikawa

Sumitomo Electric Industries

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Kenichi Hirotsu

Sumitomo Electric Industries

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Takashi Hoshino

Sumitomo Electric Industries

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Shin Harada

Sumitomo Electric Industries

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Hiroyuki Matsunami

Sumitomo Electric Industries

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Takashi Tsuno

Sumitomo Electric Industries

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Tsunenobu Kimoto

Sumitomo Electric Industries

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Hideto Tamaso

Sumitomo Electric Industries

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Hitoki Tokuda

Sumitomo Electric Industries

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Kazuyuki Wada

Toyohashi University of Technology

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