Shizuo Sawada

A 45-ns 16-Mbit DRAM with triple-well structure

The authors describe a 16-Mb DRAM (dynamic RAM) fabricated with a triple-well CMOS technology that enables optimum choice of well bias. With this technology, an optimized chip architecture, and a p-channel load word-line bootstrap driver incorporating a predecoder a 45-ns row-access-strobe access time is achieved. The memory cell is in a quarter-pitched arrangement combined with an interdigitated bit-line/shared-sense-amplifier scheme. This overcomes the difficulty of defining capacitor-plate poly in a scaled-down trench or buried-stacked-capacitor cell. The output waveform of the RAM is shown. The features of the 16M DRAM are summarized. It is capable of fast page, static column, or nibble operation and -*1- or *4-bit organization, determined by the choice of bonding configuration.<<ETX>>

Stacked capacitor cells for high-density dynamic RAMs

A novel process sequence fabricating stacked capacitor cells has been developed for high-density dynamic RAMs (random access memories). Enhanced cell capacitance can be obtained by opening the contact window for the lower electrode of the stacked capacitor after the deposition of the electrode poly-Si. This is followed by additional substrate Si etching. The procedure results in sufficient cell capacitance even in 64-Mb dynamic RAMs.<<ETX>>

Embedded DRAM technologies

Issues on embedded DRAM technologies including their applications, process options, and tradeoffs are discussed. Real implementations of the embedded DRAM technologies with 0.5 /spl mu/m, 0.35 /spl mu/m, and 0.25 /spl mu/m are also presented. The embedded DRAM technologies will be used to realize high bandwidth and low power operation.

A 1Mb CMOS DRAM with fast page and static column modes

1Mw X l b CMOS DRAM with 24ns column address access time, 56ns row access time, 30mA average active current and 0.3mA CMOS standby current will be described. The chip has been fabricated with a 1 . 2 ~ triple-polysilicon N-well CMOS process. The RAM uses a half Vcc bit line precharge technique with a complementary capacitor coupled dummy cell (C3DC) and a bit-line level generator to reduce by 50% the bit-line discharge current and also to improve the sensing margin. Figure 1 shows sense circuit schematics and pulse diagrams. At the beginning of an active cycle, the selected word line is bootstrapped above the Vcc level to obtain a large signal from the memory cell for speed and to store full Vcc potential in the memory cell for a high sensing margin. At the same time, one of the dummy word-line pairs, precharged to a half Vcc level, goes to full Vcc level, while the other to Vss level, setting the reference bit line to correct mid-point level. During the active cycle after sensing, one of the bit line pair is kept at full Vcc level by a P-channel restoring circuit, while the other is kept at Vss level by an Nchannel sense amplifier. At the end of the active cycle, bit line pairs as well as dummy word lines are short-circuited and equalized to the half Vcc level without discharge. In addition, the half Vcc level (VBL) generated by the bit-line level generator is supplied to these bit-line pairs and dummy word lines to eliminate unbalance due to the leakage current during RAS precharge cycle. The bit-line equalizing technique in the RAS precharge cycle permits access to the high speed memory cell. Another feature of the development is the use of partial activation of the memory array that is divided into 4 blocks. Two blocks out of four are selectively activated in each cycle, leaving the other two blocks in a standby condition. Therefore, the power dissipation due to the bit-line discharge/precharge operation is reduced to about 1/4 by the half Vcc bit-line precharge and the partial activation. A substrate bias generator with a VBB level detection circuit controls the ring oscillator. The VBB level goes down quickly at power on time, t o increase the latch-up immunity, and the low standby current is realized at a stable state. The use of clocked CMOS circuits and asynchronous CMOS static circuits with address transition detectors for high speed operation is shown in Figure 2. The flexibility inherent to CMOS circuitry permits the inclusion of fast page and the static column modcs with a metal mask option. Laser redundancy circuits improve fabrication yield without speed degradation and minimize the number of fuse links. Four spare columns and four spare rows are available to replace defective bits, rows and columns.

Measurement of intrinsic capacitance of lightly doped drain (LDD) MOSFET's

Intrinsic capacitance of lightly doped drain (LDD) MOSFETs is measured by means of a four-terminal method without using any on-chip measurement circuits. The gate-to-drain capacitance Cgdof LDD MOSFETs is smaller than that of conventional MOSFETs in the saturation region. The technique is applied to determine the effective channel length.

Oxidation rate reduction in the submicrometer LOCOS process

Experimental and analytical studies on submicrometer LOCOS oxide structures have been carried out. LOCOS oxide thickness reduction in submicrometer nitride windows has been newly observed. However, the birds beak length remains constant, in spite of decreasing the nitride window to 0.3 µm. In order to explain these results, a simple oxidation model is experimentally introduced that considers the lateral diffusion of oxidants from the nitride edge. Oxide thickness reduction is due to the decrease of oxidants in the submicrometer nitride window. A locus for the isolation region length in the etched back LOCOS process is also given by using our model. The nitride window sensitivity for LOCOS oxide structures should be considered during the process design for miniature devices with a submicrometer feature size.

Hot-carrier injection suppression due to the nitride-oxide LDD spacer structure

The hot-carrier effects in silicon nitride lightly doped drain (LDD) spacer MOSFETs are discussed. It is found that the oxide thickness under the nitride film spacer affects the hot-carrier effects. The thinner the LDD spacer oxide becomes, the larger the initial drain current degradation becomes at the DC stress test and the smaller the stress time dependence becomes. After the DC stress test, reduced drain current recovers at room temperature. These phenomena are due to the large hot-carrier injection into the LDD nitride spacer, because the nitride film barrier height is much less than the silicon oxide barrier height. Therefore, it is necessary to form the LDD spacer oxide, in order to suppress the large hot-carrier injection in the nitride film LDD spacer MOSFET. The drain current shift mechanism in the nitride spacer MOSFETs is discussed, considering the lucky electron model. >

A 17-ns 4-Mb CMOS DRAM

A 17-ns nonaddress-multiplexed 4-Mb dynamic RAM (DRAM) fabricated with a pure CMOS process is described. The speed limitations of the conventional DRAM sensing technique are discussed, and the advantages of using the direct bit-line sensing technique are explained. A direct bit-line sensing technique with a two-stage amplifier is described. One readout amplifier is composed of a two-stage current-mirror amplifier and a selected readout amplifier is activated by a column decoder output before the selected word line rises. The amplifier then detects a small bit-line signal appearing on a bit-line pair immediately after the word-line rise. This two-stage amplification scheme is essential to improving access time, especially in the case of a CMOS process. The high sensitivity of the readout amplifier is discussed, and the electrical features and characteristics of the fabricated DRAM are reported. >

New degradation phenomena by source and drain hot-carriers in half-micron P-MOSFETs

Hot-carrier phenomena in half-micron offset type P-MOSFETs have been investigated, comparing to that of conventional ones with the same effective channel length. At high gate bias stress test, it is newly found that injected source hot-holes cause large minus Vthshift in the forward mode measurement. In addition, in the drain region, double injections of hot-electron and hot-hole occurs. As a result, Vthshift in the reverse mode changes from plus to minus with stress time. As source hot-holes are considered to affect the reliability of actual CMOS circuits, it as important to introduce the LDD structure into half-micron P-MOSFETs to reduce the high electric field in the source region.

Effects of field boron dose on substrate current in narrow channel LDD MOSFETs

Effects of field boron dose on substrate currents in narrow channel LDD NMOSFETs are investigated. When field boron is heavily introduced, the substrate peak currents show marked increase. Through experiments and simulation, it was found that the increase of the substrate peak current in wide channel device is due to the generation of hot carrier at the isolation edges and that a marked hump of substrate peak current in narrow channel device is mainly due to the increase of impact ionization rate at the center of channel region. These phenomena are explained by the field boron penetration toward the channel region. It is also shown that the increase of substrate peak current in narrow channel LDD MOSFETs gives rise to the degradation of current drive capability.