Masami Konaka

A 1024-bit MNOS RAM using avalanche-tunnel injection

MNOS memory cells which consist of one MNOS transistor and two MOS transistors are incorporated into a fully decoded 1024-word by 1-bit random access memory (RAM) with nonvolatility. The features of the present nonvolatile RAM are: 1) by introducing a novel mode of write operation, electrical isolators, such as p-n junction isolation between the memory cells and the other circuits are not required, 2) stored data can last more than one year without any kind of external power supply, 3) the chip size of the memory is 3.60/spl times/3.61 mm/SUP 2/, 4) the read-access time is 600 ns and the write cycle time is 10 /spl mu/s-100 /spl mu/s.

Design Limitations due to Substrate Currents and Secondary Impact lonization Electrons in NMOS LSI's

A quantitative analysis of the substrate current and its secondary effects in NMOS LSIs are described. The substrate current is accurately calculated by a two-dimensional numerical analysis for short channel transistors down to 1 µm channel length. Minority carrier injection in substrate, which results from a secondary impact ionization, is also studied. The minority carrier current in the substrate is measured using a CCD test device, and is found to be nearly proportional to the substrate current. A physical model for these phenomena is also presented. Minority carrier injection efficiency is then given by an empirical equation as a function of effective channel length. Based on the models and experimental results, limiting voltages for MOS LSIs are estimated in terms of punch-through, parasitic bipolar transistor breakdown, excess electrons and hot electron trapping.

Two dimensional nature of diffused line capacitance in coplanar MOS structures

Two dimensional nature of diffused line capacitance in the coplanar MOS LSI structure is investigated delineating importance of the side wall capacitance with decreasing feature size of devices. The effects of field channel stop ion implantation on the narrow channel effect, the field MOS threshold voltage and the junction breakdown voltage are also discussed toward optimization of coplanar process parameters.

Anomalous drain current in n-MOSFET's and its suppression by deep ion implantation

Effects of the deep ion implantation on the characteristics of the short channel n-MOSFET have been investigated by two-dimensional numerical analysis and verified experimentally. By the analysis, it has been found that the anomalous drain current which flows in the relatively deep region between the source and the drain has been effectively suppressed by the deep ion implantation of acceptor impurities into the channel region. Structure of short channel n-MOSFET with deep ion-implanted layer has been optimized by computer simulation to suppress the anomalous drain current. Experimentally, the low and steep subthreshold current characteristics have been obtained by deep ion implantation for short channel n-MOSFETs with LEFF= 1.2µm. Furthermore, the back gate bias dependence of the threshold voltage of the implanted short channel device can be made almost likely to that of the unimplanted long channel device.

Two-Dimensional Nature of Diffused Layers and Certain Limitations in Scaling-Down Coplanar Structure

Limitation of the coplanar technology to geometry miniaturization has been investigated. Two-dimensional nature of diffused line capacitance in a coplanar structure is investigated for the first time delineating importance of the sidewall capacitance with decreasing feature size of devices. The effects of field channel-stop ion implantation on the narrow-channel effect, the field MOS threshold voltage, and the junction breakdown voltage are also discussed.