Tomohisa Mizuno

Experimental study of threshold voltage fluctuation due to statistical variation of channel dopant number in MOSFET's

Threshold voltage fluctuation has been experimentally studied, using a newly developed test structure utilizing an 8 k-NMOSFET array. It has been experimentally shown that both V/sub th/ and the channel dopant number n/sub a/ distributions are given as the Gaussian function, and verified that the standard deviation of n/sub a/, can be expressed as the square root of the average of n/sub a/, which is consistent with statistics. In this study, it has been shown that V/sub th/ fluctuation (/spl delta/V/sub th/) is mainly caused by the statistical fluctuation of the channel dopant number which explains about 60% of the experimental results. Moreover, we discuss briefly a new scaling scenario, based on the experimental results of the channel length, the gate oxide thickness, and the channel dopant dependence of /spl delta/V/sub th/. Finally, we discuss V/sub th/ fluctuation caused by the independent statistical-variations of two different dopant atoms in the counter ion implantation process. >

Electron and hole mobility enhancement in strained-Si MOSFET's on SiGe-on-insulator substrates fabricated by SIMOX technology

We have newly developed strained-Si MOSFETs on a SiGe-on-insulator (strained-SOI) structure fabricated by separation-by-implanted-oxygen (SIMOX) technology. Their electron and hole mobility characteristics have been experimentally studied and compared to those of control SOI MOSFETs. Using an epitaxial regrowth technique of a strained-Si film on a relaxed-Si/sub 0.9/Ge/sub 0.1/ layer and the conventional SIMOX process, strained-Si (20 nm thickness) layer on fully relaxed-SiGe (340 nm thickness)-on-buried oxide (100 nm thickness) was formed, and n-and p-channel strained-Si MOSFETs were successfully fabricated. For the first time, the good FET characteristics were obtained in both n-and p-strained-SOI devices. It was found that both electron and hole mobilities in strained-SOI MOSFETs were enhanced, compared to those of control SOI MOSFETs and the universal mobility in Si inversion layer.

Channel structure design, fabrication and carrier transport properties of strained-Si/SiGe-on-insulator (strained-SOI) MOSFETs

This paper reviews the current critical issues regarding the device design of strained-Si MOSFETs and demonstrates that strained-Si-on-insulator (strained-SOI) structures can effectively solve these problems. The advantages, characteristics and challenges of strained-SOI CMOS technology are presented, on the basis of our recent results. Furthermore, a future possible direction of channel engineering using strained-Si/SiGe structures, into the deep sub-100 nm regime, is addressed.

High performance strained-Si p-MOSFETs on SiGe-on-insulator substrates fabricated by SIMOX technology

We have proposed a new MOSFET structure, strained-Si/Si/sub 0.9/Ge/sub 0.1/-on-Insulator (SSGOI) MOSFETs applicable to the sub-100 nm generation. This SSGOI structure was successfully fabricated by the combination of SIMOX technology and the Si re-growth technique. The strained-Si in SSGOI was found to have good crystal quality and very flat interfaces. SSGOI p-MOSFETs exhibited good FET characteristics. It was demonstrated, for the first time, that the hole mobility of the SSGOI p-MOSFETs is higher that of the universal mobility of conventional Si p-MOSFETs.

[110]-surface strained-SOI CMOS devices

We have newly developed [110]-surface strained-silicon-on-insulator (SOI) n- and p-MOSFETs on [110]-surface relaxed-SiGe-on-insulator substrates with the Ge content of 25%, fabricated by applying the Ge condensation technique to SiGe layers grown on [110]-surface SOI wafers. We have demonstrated that the electron and the hole mobility enhancement of [110]-surface strained-SOI devices amounts to 23% and 50%, respectively, against the mobilities of [110]-surface unstrained MOSFETs. As a result, the electron and the hole mobility ratios of [110]-surface strained-SOI MOSFETs to the universal mobility of (100)-surface bulk-MOSFETs increase up to 81% and 203%, respectively. Therefore, the current drive imbalance between n- and p-MOS can be reduced. Moreover, both the electron and the hole mobilities of the [110]-surface strained-SOIs strongly depend on the drain current flow direction, which is qualitatively explained by the anisotropic effective mass characteristics of the carriers on a [110]-surface Si. As a result, the [110]-surface strained-SOI technology with optimization of the current flow directions of n- and p-MOS is promising for realizing higher speed scaled CMOS.

Advanced SOI-MOSFETs with strained-Si channel for high speed CMOS-electron/hole mobility enhancement

In this work, we propose strained-Si MOSFETs on double-layer SiGe films with different Ge contents as high performance p-MOSFETs. Actually, we demonstrate high hole mobility enhancement (45% against that in control-SOI MOSFETs and 30% against the universal mobility) in strained-SOI p-MOSFETs including double-hetero structures (Si/sub 0.82/Ge/sub 0.18//Si/sub 0.9/Ge/sub 0.1/) for the first time. Moreover, it is also demonstrated that the electron mobility in n-channel strained-SOI MOSFETs is enhanced by about 60%, using single SiGe layer with the Ge content of as low as 10%.

Temperature effects on Ge condensation by thermal oxidation of SiGe-on-insulator structures

The Ge depth profile and generation of dislocations associated with oxidation of SiGe-on-insulator (SGOI) substrates are examined from the viewpoint of the temperature dependence. It is found that Ge profiles in SGOI layers after oxidation are strongly dependent on the oxidation temperature. This fact is explained by the competitive process between the accumulation of Ge atoms at the SiGe/thermal oxide interface, determined by the oxidation rate, and Ge diffusion toward substrates during oxidation of SGOI substrates. While the abrupt Ge profile obtained by low-temperature oxidation causes the generation of dislocations, SGOI layers with high Ge content and no dislocations can be achieved by high-temperature oxidation.

Ultrathin body SiGe-on-insulator pMOSFETs with high-mobility SiGe surface channels

A novel concept and a fabrication technique of strained SiGe-on-insulator (SGOI) pMOSFET are proposed and demonstrated. This device has an ultrathin strained SiGe channel layer, which is directly sandwiched by gate oxide and buried oxide layers. The mobility enhancement of 2.3 times higher than the universal mobility of conventional universal Si pMOSFETs was obtained for a pMOSFET with 19-nm-thick Si/sub 0.58/Ge/sub 0.42/ channel layer, which is formed by high-temperature oxidation of a Si/sub 0.9/Ge/sub 0.1/ layer grown on a Si-on-insulator (SOI) substrate. A fully depleted SGOI MOSFET with this simple single-layer body structure is promising for scaled SOI p-MOSFET with high current drive.

Advanced SOI p-MOSFETs with strained-Si channel on SiGe-on-insulator substrate fabricated by SIMOX technology

We have newly developed an advanced SOI p-MOSFET with strained-Si channel on insulator (strained-SOI) structure fabricated by SIMOX (separation-by-implanted-oxygen) technology. The characteristics of this strained-SOI substrate and electrical properties of strained-SOI MOSFETs have been experimentally studied. Using strained-Si/relaxed-SiGe epitaxy technology and usual SIMOX process, we have successfully formed the layered structure of fully-strained-Si (20 nm)/fully-relaxed-SiGe film (290 nm) on uniform buried oxide layer (85 nm) inside SiGe layer. Good drain current characteristics have been obtained in strained-SOI MOSFETs. It is found that the hole mobility is enhanced in strained-SOI p-MOSFETs, compared to the universal hole mobility in an inversion layer and the mobility of control SOI p-MOSFETs. The enhancement of the drive current has been kept constant down to 0.3 /spl mu/m of the effective channel length.

Novel SOI p-channel MOSFETs with higher strain in si channel using double SiGe heterostructures

We have studied p-channel advanced SOI MOSFETs using double SiGe heterostructures fabricated by the combination of SIMOX and high-quality strained-Si/SiGe regrowth technologies, in order to introduce higher strain in Si channel. It was revealed that this double SiGe structure of second Si/sub 0.82/Ge/sub 0.18/Si/sub 0.93/Ge/sub 0.07/allows the second SiGe layer to relax by about 70%, because of the elastic energy balance between the second and the first-SiGe layers. As a result, the strain of Si layer on this double SiGe structure becomes higher than that of the single SiGe structure. Strained SOI p-MOSFETs using the double layer SiGe structure exhibited higher hole mobility than that of strained-SOI MOSFETs with single Si/sub 0.9/Ge/sub 0.1/ structure. The hole mobility enhancement of 30% and 45% was achieved in the strained-SOI MOSFETs with double SiGe structures, compared to that of the universal curve and the control-SOI MOSFETs, respectively.