Saurabh Sant

Band-Offset Engineering for GeSn-SiGeSn Hetero Tunnel FETs and the Role of Strain

In this paper a simulation study of the effect of conduction and valence band offsets on the subthreshold swing (SS) of a double-gate tunnel field-effect transistor (TFET) with gate-overlapped source is presented. The simulations show that if the pn-junction and the hetero-junction coincide, the band offsets can significantly improve the SS by suppressing the so-called point tunneling at the pn-junction. It turns out that the performance of an n-channel TFET is determined by the direct conduction band offset whereas that of a p-channel TFET is mainly effected by the energy difference between the light hole bands of the two materials. Thus, the performance of the hetero-junction TFET can be improved by selecting material systems with high conduction or valence band offsets. The misalignment between the pn-junction and the hetero-junction is shown to degrade the SS. The above-described band-offset engineering has been applied to the GeSn/SiGeSn hetero-structure system with and without strain. Simulations of GeSn/SiGeSn hetero-TFETs with band-to-band-tunneling parameters determined from pseudopotential calculations show that compressive strain in GeSn widens the design space for TFET application while tensile strain reduces it.

Pseudopotential calculations of strained-GeSn/SiGeSn hetero-structures

We have obtained empirical pseudopotential parameters for α-Sn and employed the pseudopotential method along with the virtual crystal approximation to model GeSn and SiGeSn alloys. The calculated direct and indirect band gaps of GeSn and SiGeSn show good agreement with experimental data at 300 K available till date. The derived pseudopotential parameter set was used to extract various band structure quantities required to model band-to-band tunneling in simulating GeSn/SiGeSn hetero-junction Tunnel Field Effect Transistors (TFET). All the required band structure quantities have been extracted as a function of biaxial strain, Si content, and Sn content and have been fitted to a quadratic expression. An attempt to simulate Si0.5Ge0.5/Si hetero-junction TFETs based on the extracted band structure quantities yields ID − VG plots that are in good agreement with the experimental ones—an indication for the reliability of the extracted band structure quantities. Thus, the calculated pseudopotential and extracted ...

Lateral InAs/Si p-Type Tunnel FETs Integrated on Si—Part 2: Simulation Study of the Impact of Interface Traps

This part of the paper presents TCAD simulations of the InAs/Si lateral nanowire (NW) tunnel FET (TFET) with the same geometry as the fabricated device discussed in the first part. In addition to band-to-band tunneling, trap-assisted tunneling (TAT) at the InAs/Si and InAs/oxide interfaces was considered. A very good agreement is found between the simulation results and experimental transfer characteristics of different devices. The simulations confirm that the transfer characteristics in the subthreshold regime of the TFETs are entirely dominated by TAT. Due to the high concentration of generation centers at the InAs/Si interface, the current conduction in the subthreshold regime takes place in two steps: carrier generation by TAT at the InAs/Si interface followed by thermionic emission over the hole barrier. The latter is the limiting process, and hence dominant for the subthreshold swing (SS), preventing a value smaller than 60mV/decade. In addition, traps at the Si/oxide interface reduce the electrostatic coupling between the gate and the channel, which further degrades the SS. Predictive simulations with varying interface trap densities indicate that a sub-thermal SS would only be achievable for Dit <; 5 x 1011 cm-2eV-1 at both InAs/Si and InAs/oxide interfaces. This confirms a recently found minimum requirement of Dit <; 1 x 1012 cm-2eV-1 for vertical InAs/Si NW TFETs with larger diameters.

Methods to Enhance the Performance of InGaAs/InP Heterojunction Tunnel FETs

This paper presents a simulation study of In0.53Ga0.47As/InP heterojunction gate-overlapped-source tunnel FETs (GoS-TFETs) with pocket counter-doping. The effect of channel quantization on the line tunneling is considered in the semiclassical simulations using a new model that modifies the band edge in the inversion layer. The small bandgap of the source material In0.53Ga0.47As results in an improved tunnel rate, while the wide bandgap of the channel/drain material InP reduces ambipolar leakage. The simulations show that, for the case of perfectly aligned p-n-junction and heterojunction, the type-I band alignment and the large band offsets delay suppress lateral (point) tunneling relative to vertical (line) tunneling which improves the subthreshold swing (SS). The counter-doped pocket in the source region advances the onset of line tunneling relative to point tunneling which also assists in mitigating the effects of point tunneling. In this way, both large band offset and counter-doped pocket improve the subthreshold behavior of the TFET. Placing the p-n-junction inside the InP region makes the vertical tunneling even more dominant and, thus, reduces the SS. The suggested modifications might be useful to improve the device performance beyond that of the conventional GoS-TFETs.

III–V-based hetero tunnel FETs: A simulation study with focus on non-ideality effects

We present semi-classical simulations of Gate-overlapped-Source Tunnel Field Effect Transistors (GoS-TFETs) taking into account the effects of trap-assisted tunneling, channel quantization, surface roughness, and density-of-state tails.

Individual Defects in InAs/InGaAsSb/GaSb Nanowire Tunnel Field-Effect Transistors Operating below 60 mV/decade

Tunneling field-effect transistors (TunnelFET), a leading steep-slope transistor candidate, is still plagued by defect response, and there is a large discrepancy between measured and simulated device performance. In this work, highly scaled InAs/InxGa1-xAsySb1-y/GaSb vertical nanowire TunnelFET with ability to operate well below 60 mV/decade at technically relevant currents are fabricated and characterized. The structure, composition, and strain is characterized using transmission electron microscopy with emphasis on the heterojunction. Using Technology Computer Aided Design (TCAD) simulations and Random Telegraph Signal (RTS) noise measurements, effects of different type of defects are studied. The study reveals that the bulk defects have the largest impact on the performance of these devices, although for these highly scaled devices interaction with even few oxide defects can have large impact on the performance. Understanding the contribution by individual defects, as outlined in this letter, is essential to verify the fundamental physics of device operation, and thus imperative for taking the III-V TunnelFETs to the next level.

Lateral InAs/Si p-Type Tunnel FETs Integrated on Si—Part 1: Experimental Devices

Tunnel FETs (TFETs) have been identified as the most promising steep slope devices for ultralow power logic circuits. In this paper, we demonstrate in-plane InAs/Si TFETs monolithically integrated on Si, using our recently developed template-assisted selective epitaxy approach. These devices represent some of the most scaled TFETs with dimensions of less than 30 nm, combined with excellent aggregate performance with average subthreshold swing (SS), of around 70 mV/decade combined with ION of a few μA/μm for |VDS| = |VGS| = 0.5 V. Here, we will discuss the device fabrication as well as the experimental electrical data. Extensive low temperature characterization and activation energy analysis is used to gain insights into the factors limiting device performance. Combined with the simulation study presented in part 2 of this paper, this will elucidate how traps are ultimately limiting the SS.

Impact of trap-assisted tunneling and channel quantization on InAs/Si hetero Tunnel FETs

As a potential candidate for solid-state switches in low-power electronic circuits, the Tunnel Field Effect Transistor (TFET) has attracted the attention of device designers in the past few years. Although simulations have shown that ideal hetero TFETs can achieve sub-thermal sub-threshold swing (SS), the fabrication of a TFET with sufficient on-current and sub-thermal SS over a few decades of drain current remains to be done. Non-idealities in a TFET such as interface traps, band tails, or surface roughness exhibit stronger influence on TFET characteristics in the sub-threshold region. In Ref. [1] we observed that among all of these non-idealities the strongest effect is due to interface traps. On the other hand, simulations have shown that channel quantization severely degrades the on-current [2]. In this work, we analyse experimental transfer characteristics of InAs/Si nanowire TFETs (diameter ≈ 100 nm) and find reasons for the degradation of SS and on-current. We give an estimate for the Dit that still would allow a sub-thermal SS.

Analysis of GeSn-SiGeSn hetero-tunnel FETs

Among the alloys of Group IV semiconductors the Germanium-Tin (GeSn) alloy is particularly interesting as it exhibits a small and direct band gap for a certain range of Sn content. This feature can be exploited for high-performance tunnel FET (TFET) application. The small direct band gap enhances the band-to-band-tunneling (BTBT) rate which results in a high on-current. In order to reduce the off-state leakage, Silicon-Germanium-Tin (SiGeSn) alloys can be used in the drain region of the TFET. Addition of Si to GeSn increases the band gap of the alloy, thus reducing the ambipolar behavior. Therefore, the GeSn/SiGeSn hetero-structure system is a promising candidate for TFET application. In this work, the performance of GeSn/SiGeSn TFETs is studied by combining the empirical pseudopotential method (EPM) with 2D/3D technology-computer-aided-design (TCAD) simulations of realistic geometries.

Manipulating Surface States of III–V Nanowires with Uniaxial Stress

III-V compound semiconductors are indispensable materials for todays high-end electronic and optoelectronic devices and are being explored for next-generation transistor logic and quantum technologies. III-V surfaces and interfaces play the leading role in determining device performance, and therefore, methods to control their electronic properties have been developed. Typically, surface passivation studies demonstrated how to limit the density of surface states. Strain has been widely used to improve the electronic transport properties and optoelectronic properties of III-Vs, but the potential of this technology to modify the surface properties still remains to be explored. Here we show that uniaxial stress induces a shift in the energy of the surface states of III-V nanowires, modifying their electronic properties. We demonstrate this phenomenon by modulating the conductivity of InAs nanowires over 4 orders of magnitude with axial strain ranging between -2.5% in compression and 2.1% in tension. The band bending at the surface of the nanostructure is modified from accumulation to depletion reversibly and reproducibly. We provide evidence of this physical effect using a combination of electrical transport measurement, Raman spectroscopy, band-structure modeling, and technology computer aided design (TCAD) simulations. With this methodology, the deformation potentials for the surface states are quantified. These results reveal that strain technology can be used to shift surface states away from energy ranges in which device performance is negatively affected and represent a novel route to engineer the electronic properties of III-V devices.