Thaddeus J. Gabara

Digitally adjustable resistors in CMOS for high-performance applications

Methods by which CMOS circuits can be adjusted digitally to generate controlled impedances for use in high-performance circuits are described. Since digital signals are the only inputs to these circuits, on-chip DC power dissipation can be reduced, the circuit can be made more robust, and the impedance of the circuit can be adjusted by manipulating the input digital information. A design of a CMOS series terminated line driver is discussed, and the utilization of the controlled impedance in terminating transmission lines on-chip, constant delay lines, and controlled di/dt output buffers is discussed. >

A 15-mW, 155-Mb/s CMOS burst-mode laser driver with automatic power control and end-of-life detection

A burst-mode laser driver for passive optical networks (ATM-PON/FSAN, N-PON, π-PON) uses mixed-signal design techniques in digital 0.5-μm CMOS. Power consumption is 15 mW, which is about an order of magnitude less than previous designs. The laser driver features automatic power control and laser end-of-life detection. These features are implemented with a novel peak comparator, which operates on a packet-by-packet basis.

Forming damped LRC parasitic circuits in simultaneously switched CMOS output buffers

Measurements of a 0.5 /spl mu/m CMOS testchip using several techniques have demonstrated a reduction in the generation of ground bounce. These techniques are: an automatic transistor sizing method that compensates for process, temperature, and supply voltage variations; a self-adjusting internal capacitive load that counteracts the increased switching rate of faster parts; and an integrated resistive element inserted directly into the power and ground leads that dampens the RLC oscillations. Comparison measurements between a conventional buffer and the new buffer have demonstrated that the amplitude and duration of the generated ground bounce has been reduced 2.5/spl times/ and 2/spl times/, respectively. A single external resistor is required to set a reference current.

Reduced ground bounce and improved latch-up suppression through substrate conduction

The conventional method of bond wiring V/sub ss/ pads on CMOS chips is examined. For p-type epitaxial CMOS on a p/sup +/ substrate, these V/sub ss/ pads may not be required. Instead, the conduction path would be through the substrate to the ground plane on the package. This technique reduces the ground bounce and improves latch-up suppression. Furthermore, for input/output (I/O) bound chips, the substrate conduction method reduces the size of the I/O frame, reduces cost by decreasing die size, and improves performance by reducing conductor lengths on the chip. An ADVICE comparison was performed between the conventional and substrate conduction methods for connection V/sub SS/ to a CMOS chip in 0.9- mu m technology. Results of packaged-chip measurements are also presented. >

LVDS I/O buffers with a controlled reference circuit

A controlled reference circuit maintains the output voltage levels and current values of an LVDS output buffer constant over (PVT) processing, voltage supply, and temperature variations. The reference circuit requires one external resistor and generates two DC control voltages which are applied to all output buffers. An on-chip resistance is described which maintains a tightly controlled impedance of approximately 100 /spl Omega/ over the common mode range of 0 to 2.4 V. A measured waveform at 1.244 Gb/s is given.

150/30 Mb/s CMOS non-oversampled clock and data recovery circuits with instantaneous locking and jitter rejection

Two 0.9 /spl mu/m CMOS chips serve for burst-mode clock and data recovery applications specific to passive optical network (PON) systems. In each case, a core, first order clock recovery circuit is realized by two gated ring oscillators, indirectly frequency-tuned by a phase-locked loop using a third replica oscillator and a local reference signal. Instantaneous phase locking is guaranteed by restarting the gated oscillators every time input data transitions occur. This method has been demonstrated to be precise enough to handle input data patterns containing hundreds of bits between transitions without errors. In addition, the circuit is small and dissipates low power. However, the recovered clock signal thus obtained inherits all jitter present in the input data signal. This shortcoming has been overcome in the present designs by two different methods. The results are the total elimination of jitter propagation and the generation of clean data and clock output signals. The first chip operates at 150 Mb/s. Since the data is demultiplexed into 8 channels, the local reference signal runs eight times slower than the transmission rate. This allows ample time for jitter-rejection processing. The second chip operates at 30 Mb/s without a demultiplexer. The jitter rejection is accomplished with an elastic store based on five 1 b registers.

Trends in silicon-on-silicon multichip modules

Three example applications of silicon-on-silicon multichip modules are discussed: a module used in a parallel processor, a low-cost silicon module for a high-volume consumer product application, and a high-performance digital telecommunications module. These applications illustrate the changes occurring in this technology and the forces that are driving these changes.<<ETX>>

Metastability of CMOS master/slave flip-flops

The authors present circuit techniques used to improve the mean time between failures (MTBF) of a latch due to metastable events. The complete approach includes a unique design of the latch and the formation of series-connected master/slave (M/S) flip-flops using this latch. An equation is developed to predict the MTBF due to metastability of a single latch and is extended to include single and multiple series connected M/S flip-flops. The equation predicts that the MTBF increases significantly by using such a M/S flip-flop configuration.<<ETX>>

An I/O CMOS buffer set for silicon multichip module's (MCM)

A set of I/O CMOS buffers for MCM is described. When simulation results of the MCM buffers are compared against conventional standard cell CMOS buffers, several advantages emerge. The results indicate that the new buffers dissipate 5 times less power, reduce propagation delay from chip core to another core from 3-6 nsec, and increase the frequency of operation by 2.5 times when compared to conventional CMOS buffers. Actual measurements between these buffers confirm these simulation results.<<ETX>>

On-chip terminating resistors for high speed ECL-CMOS interfaces

A method of forming on-chip resistors in CMOS technology from active and passive devices is described. These resistors can be used to terminate 100 K ECL transmission lines. An external resistor is required to establish a reference point. The area of these on-chip resistors is 30 by 125 mu m, does not require trimming, and has the advantage that these chips could be housed inside a cheaper package.<<ETX>>