Scott D. Kee

Fully integrated CMOS power amplifier design using the distributed active-transformer architecture

A novel on-chip impedance matching and power-combining method, the distributed active transformer is presented. It combines several low-voltage push-pull amplifiers efficiently with their outputs in series to produce a larger output power while maintaining a 50-/spl Omega/ match. It also uses virtual ac grounds and magnetic couplings extensively to eliminate the need for any off-chip component, such as tuned bonding wires or external inductors. Furthermore, it desensitizes the operation of the amplifier to the inductance of bonding wires making the design more reproducible. To demonstrate the feasibility of this concept, a 2.4-GHz 2-W 2-V truly fully integrated power amplifier with 50-/spl Omega/ input and output matching has been fabricated using 0.35-/spl mu/m CMOS transistors. It achieves a power added efficiency (PAE) of 41 % at this power level. It can also produce 450 mW using a 1-V supply. Harmonic suppression is 64 dBc or better. This new topology makes possible a truly fully integrated watt-level gigahertz range low-voltage CMOS power amplifier for the first time.

Distributed active transformer-a new power-combining and impedance-transformation technique

In this paper, we compare the performance of the newly introduced distributed active transformer (DAT) structure to that of conventional on-chip impedance-transformations methods. Their fundamental power-efficiency limitations in the design of high-power fully integrated amplifiers in standard silicon process technologies are analyzed. The DAT is demonstrated to be an efficient impedance-transformation and power-combining method, which combines several low-voltage push-pull amplifiers in series by magnetic coupling. To demonstrate the validity of the new concept, a 2.4-GHz 1.9-W 2-V fully integrated power-amplifier achieving a power-added efficiency of 41% with 50-/spl Omega/ input and output matching has been fabricated using 0.35-/spl mu/m CMOS transistors.

The class-E/F family of ZVS switching amplifiers

A new family of switching amplifiers, each member having some of the features of both class E and inverse F, is introduced. These class-E/F amplifiers have class-E features such as incorporation of the transistor parasitic capacitance into the circuit, exact truly switching time-domain solutions, and allowance for zero-voltage-switching operation. Additionally, some number of harmonics may be tuned in the fashion of inverse class F in order to achieve more desirable voltage and current waveforms for improved performance. Operational waveforms for several implementations are presented, and efficiency estimates are compared to class-E.

A Fully Integrated Quad-Band GSM/GPRS CMOS Power Amplifier

Concentric distributed active transformers (DAT) are used to implement a fully-integrated quad-band power amplifier (PA) in a standard 130 nm CMOS process. The DAT enables the power amplifier to integrate the input and output matching networks on the same silicon die. The PA integrates on-chip closed- loop power control and operates under supply voltages from 2.9 V to 5.5 V in a standard micro-lead-frame package. It shows no oscillations, degradation, or failures for over 2000 hours of operation with a supply of 6 V at 135degC under a VSWR of 15:1 at all phase angles and has also been tested for more than 2 million device-hours (with ongoing reliability monitoring) without a single failure under nominal operation conditions. It produces up to +35 dBm of RF power with power-added efficiency of 51%.

A Fully-Integrated Quad-Band GSM/GPRS CMOS Power Amplifier

Concentric distributed active transformers (DAT) are used to implement a fully-integrated quad-band power amplifier (PA) in a standard 130 nm CMOS process. The DAT enables the power amplifier to integrate the input and output matching networks on the same silicon die. The PA integrates on-chip closed- loop power control and operates under supply voltages from 2.9 V to 5.5 V in a standard micro-lead-frame package. It shows no oscillations, degradation, or failures for over 2000 hours of operation with a supply of 6 V at 135degC under a VSWR of 15:1 at all phase angles and has also been tested for more than 2 million device-hours (with ongoing reliability monitoring) without a single failure under nominal operation conditions. It produces up to +35 dBm of RF power with power-added efficiency of 51%.

An optimized design of distributed active transformer

A novel structure distributed active transformer (DAT), which significantly reduces the coupling from the DAT to the feed line is demonstrated. A grounded guard line is implemented to isolate the feed line from the magnetic field of the DAT. The measured result of the DAT on a GaAs substrate shows a 10.5-dB reduction in the coupling. To reduce DAT loss, an air-bridge connected double primary DAT structure is implemented. The DAT at 2 GHz shows a 0.7-dB loss reduction in comparison to the conventional DAT. The improved DAT performance is related to the reduced metal resistance and closer coupling between the primary and secondary loops without any increase in the DAT area.

A fully-integrated 1.8-V, 2.8-W, 1.9-GHz, CMOS power amplifier

This paper demonstrated the first 2-stage, 2.8 W, 1.8 V, 1.9 GHz fully-integrated distributed active transformer (DAT) power amplifier with 50 /spl Omega/ input and output matching using 0.18 /spl mu/m CMOS transistors. It has a small-signal gain of 27 dB. The amplifier provides 2.8 W of power into a 50 /spl Omega/ load with a PAE of 50%.

A 2.4-GHz, 2.2-W, 2-V fully-integrated CMOS circular-geometry active-transformer power amplifier

A 2.4-GHz, 2.2-W, 2-V fully integrated circular geometry power amplifier with 50 /spl Omega/ input and output matching is fabricated using 2.5 V, 0.35 /spl mu/m CMOS transistors. It can also produce 450 mW using a 1 V supply. Harmonic suppression is 64 dB or better. An on-chip circular-geometry active-transformer is used to combine several push-pull low-voltage amplifiers efficiently to produce a larger output power while maintaining a 50 /spl Omega/ match. This new on-chip power combining and impedance matching method uses virtual AC grounds and magnetic couplings extensively to eliminate the need for any offchip component such as wirebonds. It also desensitizes the operation of the amplifier to the inductance of bonding wires and makes the design more reproducible. This new topology makes possible a fully-integrated 2.2 W, 2.4 GHz, low voltage CMOS power amplifier for the first time.

7-MHz, 1.1-kW demonstration of the new E/F/sub 2,odd/ switching amplifier class

The first switching amplifier in the new E/F/sub 2,odd/ class belonging to the new E/F/sub x/ family of switching power amplifiers has been successfully demonstrated. This push-pull amplifier exhibits 1.1 kW, 85% drain efficiency and 17 dB gain at 7 MHz. The amplifier uses low cost switching MOSFETs and fits in a small volume of only 900 cm/sup 3/ including an integrated cooling fan.

Demonstration of a switchless Class E/F/sub odd/ dual-band power amplifier

A 250 W dual-band power amplifier belonging to the Class E/F switching amplifier family is presented. The amplifier operates in the 7 MHz and 10 MHz HAM bands, achieving 16 dB and 15 dB gain with power added efficiencies (PAE) of 92% and 87% in those bands, respectively. It utilizes dual-resonant passive input and output networks to achieve high-efficiency Class E/F/sub odd/ operation at both frequencies of operation, allowing the same passive networks to be used for both frequency bands without the use of band-select switches.