Scott K. Pozder

Analytical and Numerical Modeling of the Thermal Performance of Three-Dimensional Integrated Circuits

Three-dimensional (3D) interconnection technology offers several electrical advantages, including reduced signal delay, reduced interconnect power, and design flexibility. 3D integration relies on through-silicon vias (TSVs) and the bonding of multiple active layers to stack several die or wafers containing integrated circuits (ICs) and provide direct electrical interconnection between the stacked strata. While this approach provides several electrical benefits, it also offers significant challenges in thermal management. While some work has been done in the past in this field, a comprehensive treatment is still lacking. In the current work, analytical and finite-element models of heat transfer in stacked 3D ICs are developed. The models are used to investigate the limits of thermal feasibility of 3D electronics and to determine the improvements required in traditional packaging in order to accommodate 3D ICs. An analytical model for temperature distribution in a multidie stack with multiple heat sources is developed. The analytical model is used to extend the traditional concept of a single-valued junction-to-air thermal resistance in an IC to thermal resistance and thermal sensitivity matrices for a 3D IC. The impact of various geometric parameters and thermophysical properties on thermal performance of a 3D IC is investigated. It is shown that package and heat sink thermal resistances play a more important role in determining temperature rise compared to thermal resistances intrinsic to the multidie stack. The improvement required in package and heat sink thermal resistances for a 3D logic-on-memory implementation to be thermally feasible is quantified. An increase in maximum temperature in a 3D IC compared to an equivalent system-in-package (SiP) is predicted. This increase is found to be mainly due to the reduced chip footprint. The increased memory die temperature in case of memory-on-logic integration compared to a SiP implementation is identified to be a significant thermal management challenge in the future. The results presented in this paper may be useful in the development of thermal design guidelines for 3D ICs, which are expected to help maximize the electrical benefits of 3D technology without exacerbating thermal management issues when implemented in early-stage electrical design and layout tools.

Electrical modeling and characterization of through-silicon vias (TSVs) for 3-D integrated circuits

The integration of chips in the third dimension has been explored to address various physical and system level limitations currently undermining chip performance. In this paper, we present a comprehensive analysis of the electrical properties of through silicon vias and microconnects with an emphasis on single via characteristics as well as inter-TSV capacitive and inductive coupling in the presence of either a neighboring ground tap or a grounded substrate back plane. We also analyze the impact of technology scaling on TSV electrical parasitics, and investigate the power and delay trend in 3-D interstratum IO drivers with those of global wire in 2-D circuits over various technology nodes. We estimate the global wire length necessary to produce an equivalent 3-D IO delay, a metric useful in early stage design tools for 3D floorplanning that considers the electrical characteristics of 3D connections with TSVs and microconnects.

Progress of 3D Integration Technologies and 3D Interconnects

Three dimensional stacked circuits having multiple active semiconductor levels rely on the development of strata bonding, micro connects between strata, through strata vias (TSV) and a wafer thinning process. Progress in the each of these process technologies for 3D strata stacking is opening the path to more robust and capable 3D process integrations.

Thermal modeling and design of 3D integrated circuits

3D interconnect technology has attracted significant interest in the recent past as a means for enabling faster and more efficient integrated circuits (ICs). 3D integration relies on through-silicon vias (TSVs) and bonding of multiple active layers. While this approach provides several electrical benefits, it also offers significant challenges in thermal management. While some work has been done in the past in this field, a comprehensive treatment is still lacking. In the current work, analytical and finite-element models of heat transfer in 3D electronic circuits are developed. The models are used to investigate the limits of thermal feasibility of 3D electronics and to determine the improvements required in traditional packaging in order to accommodate 3D ICs. An analytical model for temperature distribution in a multi-die stack with multiple heat sources is developed. The analytical model is used to extend the traditional concept of thermal resistance in an IC to thermal resistance and thermal sensitivity matrices for a 3D IC. The impact of various geometric parameters and thermophysical properties on thermal performance of a 3D IC is investigated. It is shown that package thermal resistances play a more important role in determining temperature rise compared to thermal resistances intrinsic to the 3D technology, including thermal resistance of bonding layers and TSVs. As a result, an improved bonding layer or TSV thermal resistance does not offer much thermal benefit. An increase in thermal resistance of a 3D IC is predicted as compared to an equivalent System-on-Chip (SoC). This increase is found to be mainly due to the reduced chip footprint. The amount of improvement required in package and heat sink thermal resistances for a logic-on-memory 3D implementation to be thermally feasible is quantified. The results presented in this paper are expected to aid in the development of thermal design guidelines for 3D ICs.

Mechanical integrity evaluation of low-k devices with bump shear

The mechanical integrity of low-k dielectric films has brought many process challenges in both front-end integration and back-end assembly, mostly due to possible interfacial delamination and fractures within the low-k films. From a packaging point of view, it is important to have an assessment of the integrity of the low-k stack before the device is fully assembled and the time-consuming full package evaluation is started. Some of the methods that are presently used to evaluate devices with low-k films either do not reflect the real stress situation in a package (such as 4-point bend), or introduce a mixed die-solder failure mode (such as die pull), which makes the results hard to interpret. In this paper, an evaluation method using solder bump shear is introduced. The solder joints are electroplated with a Cu stud as part of the under bump metallization. When the testing parameters are carefully optimized, bump shear can induce a failure in the low-k stack. By analyzing the maximum load of the shear test and the characteristics of the load curves, die with different interlayer dielectric materials and locations on the die with different interconnect metal densities can be effectively differentiated. A finite-element model is established and fracture mechanics methodologies are utilized to interpret the results of the bump shear.

Three dimensional chip stacking using a wafer-to-wafer integration

A three-dimensional (3D) wafer-to-wafer integration technology has been developed using face-to-face dielectric wafer bonding, followed by wafer thinning and backside interconnect formation. The key technologies required for this integration include: reliable defect free direct dielectric wafer bonding, precise wafer-to-wafer alignment, backside thinning, deep inter-strata via (ISV) formation, and wafer patterning alignment across strata. Electrical measurements indicate continuity of ISV chains for all but the smallest vias.

Electromigration of Cu-Sn-Cu micropads in 3D interconnect

There is significant interest in 3D interconnect technology due to its capability to provide fast, efficient inter-die interconnects at a minimum package footprint. Intermetallic Cu-Sn bonding has been widely investigated for 3D interconnects. However, the electromigration (EM) intrinsic reliability of the 3D Cu-Sn die-to-die microconnects has not been reported. In this paper the EM performance of 3D Cu-Sn microconnects formed by thermo-compression bonding is investigated and the failure mechanisms are discussed. The 3D stacked dice were assembled in wire bond ceramic packages and EM tests were conducted in both air and nitrogen ambient at various temperatures. Microconnect chain and Kelvin structures failure lifetime and the mean time to failure (MTTF) were measured. The failure analysis has been conducted and the possible failure mechanism has been proposed.

Back-end compatibility of bonding and thinning processes for a wafer-level 3D interconnect technology platform

A previously proposed wafer-level 3D IC technology platform has been extensively evaluated for compatibility with conventional IC packaging. Results demonstrate that the dielectric glue bonding using benzocyclobutene (BCB) is compatible with conventional wafer sawing techniques, and that the bond adhesion strength is unaffected by die-level autoclave and thermal shock testing. High-resolution X-ray diffraction (HRXRD) results show that the stress levels in 70 nm or 140 nm thick silicon SOI layers had no appreciable change after BCB bonding and wafer-thinning.

Thermal-electrical co-optimisation of floorplanning of three-dimensional integrated circuits under manufacturing and physical design constraints

Although the stacking of multiple strata to produce three-dimensional (3D) integrated circuits (ICs) improves interconnect length and hence reduces power and latency, it also results in the exacerbation of the thermal management challenge owing to the increased power density. There is a need for design tools to understand and optimise the trade-off between electrical and thermal design at the device and block levels. This study presents results from thermal-electrical co-optimisation for block-level floorplanning in a multi-die 3D IC under various manufacturing and physical design constraints. A method for temperature computation based on linearity of the governing energy equation is presented. This method is combined with previously reported electrical delay models for 3D ICs to simultaneously optimise both the maximum temperature and the interconnect length. It is shown that co-optimisation of thermal and electrical objectives results in a floorplan that is attractive from both perspectives. Physical design constraints because of cost-effective 3D manufacturing such as using fully or partly identical dies using reciprocal design symmetry (RDS), differentiated technology in each die and thinned die/wafer are discussed and their impact on the thermal-electrical co-optimisation is investigated. In some cases, the cheapest manufacturing choice, such as using identical die, for each layer may not result in optimal thermal and electrical design. Results presented in this work highlight the need for thermal and electrical co-design in multi-strata microelectronics, and for reconciling manufacturing and design considerations in order to develop practical design tools for 3D ICs.

3D Die-to-wafer Cu/Sn Microconnects Formed Simultaneously with an Adhesive Dielectric Bond Using Thermal Compression Bonding

The simultaneous formation of Cu/Sn microconnects and an adhesive bond during wafer level thermal compression bonding was evaluated using a 3D enabled single metal level test die and wafer. The wafer level bond process relied on locally dispensed adhesive to fix the dice to the wafer prior to bonding and to become a permanent bond during the bonding process. The die-to-wafer microconnect resistance was measured for micropad pitches of 59, 64, and 69 ¿m. The robustness of the Cu/Sn and adhesive bond was demonstrated by thinning the bonded die to 50 ¿m. Package level reliability testing of parts that were wire bonded into a thermally enhanced plastic ball grid array (PBGA) package indicates good reliability behavior and the absence of any intrinsic reliability-related issues in the microconnects.